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mir opt cross compile
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@lcnr
lcnr committed Jul 15, 2020
1 parent d4cb820 commit 9df03cc
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Showing 4 changed files with 12 additions and 12 deletions.
4 changes: 2 additions & 2 deletions src/test/mir-opt/const_prop/bad_op_unsafe_oob_for_slices/32bit/rustc.main.ConstProp.diff
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Expand Up @@ -28,10 +28,10 @@
_9 = const main::promoted[0]; // scope 0 at $DIR/bad_op_unsafe_oob_for_slices.rs:5:25: 5:35
// ty::Const
// + ty: &[i32; 3]
// + val: Unevaluated(DefId(0:3 ~ bad_op_unsafe_oob_for_slices[317d]::main[0]), [], Some(promoted[0]))
// + val: Unevaluated(WithOptParam { did: DefId(0:3 ~ bad_op_unsafe_oob_for_slices[317d]::main[0]), param_did: None }, [], Some(promoted[0]))
// mir::Constant
// + span: $DIR/bad_op_unsafe_oob_for_slices.rs:5:25: 5:35
// + literal: Const { ty: &[i32; 3], val: Unevaluated(DefId(0:3 ~ bad_op_unsafe_oob_for_slices[317d]::main[0]), [], Some(promoted[0])) }
// + literal: Const { ty: &[i32; 3], val: Unevaluated(WithOptParam { did: DefId(0:3 ~ bad_op_unsafe_oob_for_slices[317d]::main[0]), param_did: None }, [], Some(promoted[0])) }
_3 = _9; // scope 0 at $DIR/bad_op_unsafe_oob_for_slices.rs:5:25: 5:35
_2 = &raw const (*_3); // scope 0 at $DIR/bad_op_unsafe_oob_for_slices.rs:5:25: 5:35
_1 = move _2 as *const [i32] (Pointer(Unsize)); // scope 0 at $DIR/bad_op_unsafe_oob_for_slices.rs:5:25: 5:35
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4 changes: 2 additions & 2 deletions src/test/mir-opt/const_prop/slice_len/32bit/rustc.main.ConstProp.diff
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Expand Up @@ -21,10 +21,10 @@
_9 = const main::promoted[0]; // scope 0 at $DIR/slice_len.rs:5:6: 5:19
// ty::Const
// + ty: &[u32; 3]
// + val: Unevaluated(DefId(0:3 ~ slice_len[317d]::main[0]), [], Some(promoted[0]))
// + val: Unevaluated(WithOptParam { did: DefId(0:3 ~ slice_len[317d]::main[0]), param_did: None }, [], Some(promoted[0]))
// mir::Constant
// + span: $DIR/slice_len.rs:5:6: 5:19
// + literal: Const { ty: &[u32; 3], val: Unevaluated(DefId(0:3 ~ slice_len[317d]::main[0]), [], Some(promoted[0])) }
// + literal: Const { ty: &[u32; 3], val: Unevaluated(WithOptParam { did: DefId(0:3 ~ slice_len[317d]::main[0]), param_did: None }, [], Some(promoted[0])) }
_4 = _9; // scope 0 at $DIR/slice_len.rs:5:6: 5:19
_3 = _4; // scope 0 at $DIR/slice_len.rs:5:6: 5:19
_2 = move _3 as &[u32] (Pointer(Unsize)); // scope 0 at $DIR/slice_len.rs:5:6: 5:19
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8 changes: 4 additions & 4 deletions src/test/mir-opt/issue-73223/32bit/rustc.main.PreCodegen.diff
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Expand Up @@ -96,10 +96,10 @@
(_5.1: &i32) = const main::promoted[1]; // scope 3 at $SRC_DIR/libcore/macros/mod.rs:LL:COL
// ty::Const
// + ty: &i32
// + val: Unevaluated(DefId(0:3 ~ issue_73223[317d]::main[0]), [], Some(promoted[1]))
// + val: Unevaluated(WithOptParam { did: DefId(0:3 ~ issue_73223[317d]::main[0]), param_did: None }, [], Some(promoted[1]))
// mir::Constant
// + span: $SRC_DIR/libcore/macros/mod.rs:LL:COL
// + literal: Const { ty: &i32, val: Unevaluated(DefId(0:3 ~ issue_73223[317d]::main[0]), [], Some(promoted[1])) }
// + literal: Const { ty: &i32, val: Unevaluated(WithOptParam { did: DefId(0:3 ~ issue_73223[317d]::main[0]), param_did: None }, [], Some(promoted[1])) }
StorageDead(_6); // scope 3 at $SRC_DIR/libcore/macros/mod.rs:LL:COL
StorageLive(_7); // scope 3 at $SRC_DIR/libcore/macros/mod.rs:LL:COL
_7 = (_5.0: &i32); // scope 3 at $SRC_DIR/libcore/macros/mod.rs:LL:COL
Expand Down Expand Up @@ -140,10 +140,10 @@
_15 = const main::promoted[0] as &[&str] (Pointer(Unsize)); // scope 4 at $SRC_DIR/libcore/macros/mod.rs:LL:COL
// ty::Const
// + ty: &[&str; 3]
// + val: Unevaluated(DefId(0:3 ~ issue_73223[317d]::main[0]), [], Some(promoted[0]))
// + val: Unevaluated(WithOptParam { did: DefId(0:3 ~ issue_73223[317d]::main[0]), param_did: None }, [], Some(promoted[0]))
// mir::Constant
// + span: $SRC_DIR/libcore/macros/mod.rs:LL:COL
// + literal: Const { ty: &[&str; 3], val: Unevaluated(DefId(0:3 ~ issue_73223[317d]::main[0]), [], Some(promoted[0])) }
// + literal: Const { ty: &[&str; 3], val: Unevaluated(WithOptParam { did: DefId(0:3 ~ issue_73223[317d]::main[0]), param_did: None }, [], Some(promoted[0])) }
StorageLive(_18); // scope 4 at $SRC_DIR/libstd/macros.rs:LL:COL
StorageLive(_19); // scope 4 at $SRC_DIR/libstd/macros.rs:LL:COL
StorageLive(_20); // scope 4 at $SRC_DIR/libcore/macros/mod.rs:LL:COL
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8 changes: 4 additions & 4 deletions src/test/mir-opt/issue-73223/32bit/rustc.main.SimplifyArmIdentity.diff
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Expand Up @@ -153,10 +153,10 @@
_51 = const main::promoted[1]; // scope 3 at $SRC_DIR/libcore/macros/mod.rs:LL:COL
// ty::Const
// + ty: &i32
// + val: Unevaluated(DefId(0:3 ~ issue_73223[317d]::main[0]), [], Some(promoted[1]))
// + val: Unevaluated(WithOptParam { did: DefId(0:3 ~ issue_73223[317d]::main[0]), param_did: None }, [], Some(promoted[1]))
// mir::Constant
// + span: $SRC_DIR/libcore/macros/mod.rs:LL:COL
// + literal: Const { ty: &i32, val: Unevaluated(DefId(0:3 ~ issue_73223[317d]::main[0]), [], Some(promoted[1])) }
// + literal: Const { ty: &i32, val: Unevaluated(WithOptParam { did: DefId(0:3 ~ issue_73223[317d]::main[0]), param_did: None }, [], Some(promoted[1])) }
_11 = _51; // scope 3 at $SRC_DIR/libcore/macros/mod.rs:LL:COL
(_9.0: &i32) = move _10; // scope 3 at $SRC_DIR/libcore/macros/mod.rs:LL:COL
(_9.1: &i32) = move _11; // scope 3 at $SRC_DIR/libcore/macros/mod.rs:LL:COL
Expand Down Expand Up @@ -220,10 +220,10 @@
_50 = const main::promoted[0]; // scope 4 at $SRC_DIR/libcore/macros/mod.rs:LL:COL
// ty::Const
// + ty: &[&str; 3]
// + val: Unevaluated(DefId(0:3 ~ issue_73223[317d]::main[0]), [], Some(promoted[0]))
// + val: Unevaluated(WithOptParam { did: DefId(0:3 ~ issue_73223[317d]::main[0]), param_did: None }, [], Some(promoted[0]))
// mir::Constant
// + span: $SRC_DIR/libcore/macros/mod.rs:LL:COL
// + literal: Const { ty: &[&str; 3], val: Unevaluated(DefId(0:3 ~ issue_73223[317d]::main[0]), [], Some(promoted[0])) }
// + literal: Const { ty: &[&str; 3], val: Unevaluated(WithOptParam { did: DefId(0:3 ~ issue_73223[317d]::main[0]), param_did: None }, [], Some(promoted[0])) }
_25 = _50; // scope 4 at $SRC_DIR/libcore/macros/mod.rs:LL:COL
_24 = _25; // scope 4 at $SRC_DIR/libcore/macros/mod.rs:LL:COL
_23 = move _24 as &[&str] (Pointer(Unsize)); // scope 4 at $SRC_DIR/libcore/macros/mod.rs:LL:COL
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