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@androm3da
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Hello, welcome to std::simd!

It seems this pull request template checklist was created while a lot of vector math ops were being implemented, and only really applies to ops. Feel free to delete everything here if it's not applicable, or ask for help if you're not sure what it means!

For a given vector math operation on TxN, please add tests for interactions with:

  • T::MAX
  • T::MIN
  • -1
  • 1
  • 0

For a given vector math operation on TxN where T is a float, please add tests for test interactions with:

  • a really large number, larger than the mantissa
  • a really small "subnormal" number
  • NaN
  • Infinity
  • Negative Infinity

@programmerjake
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quite a lot of the library assumes the max lane count is 64, at the very least basically all the tests that only test up to 64 lanes should also test more than 64 lanes. also the bitmasks code uses u64 so is restricted to at most 64 lanes.

@programmerjake
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programmerjake commented Jan 23, 2026

getting all the tests to pass with 128 lanes is going to be a lot of work and be somewhat controversial (though we do want to increase the limit to more than 128 at some point), so if you want this PR to have a good chance of getting merged quickly, I'd suggest leaving out the change to 128 lanes and maybe just have the 1 byte x 128 lanes hexagon types be commented out for now with a fixme to re-enable them when we get around to adding support for >64 lanes.

@androm3da
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somewhat controversial

Would it be a good idea for me to create an MCP?

getting merged quickly

I'm not in a hurry.

leaving out the change to 128 lanes and maybe just have the 1 byte x 128 lanes hexagon types be commented out for now with a fixme to re-enable them when we get around to adding support for >64 lanes.

Sounds good to me: will do.

Add explicit tests for integer and float operations with edge case values
as requested by the community PR checklist:

Signed integers (MAX, MIN, -1, 1, 0):
- add, sub, mul edge cases with wrapping behavior
- bitwise ops (AND, OR, XOR, NOT) edge cases
- shift operations edge cases
- reduce operations edge cases
- abs and signum edge cases

Unsigned integers (MAX, 1, 0):
- add, sub, mul edge cases with wrapping behavior
- div, rem edge cases
- bitwise and shift operations edge cases
- reduce operations edge cases
- wrapping_neg and abs_diff edge cases

Floats (large numbers, subnormals, NaN, ±Infinity):
- arithmetic operations with special values
- NaN propagation and comparison behavior
- infinity arithmetic edge cases
- neg, abs, recip, signum, copysign edge cases
- classification functions (is_finite, is_nan, etc.)
- simd_min, simd_max with special values
- reduce operations with special values

Tests skip ARM v7 Neon for subnormal-related tests due to known
float opsem violations (issue rust-lang#439).
@androm3da
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BTW: not sure if I understood the goal of the checklist but 3e0f44c Add comprehensive edge case tests for SIMD operations was intended to handle that.

@androm3da androm3da changed the title add support for Hexagon HVX ; Increase lane limit to 128 add support for Hexagon HVX Jan 23, 2026
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2 participants