Skip to content

Commit 3033233

Browse files
bors[bot]Tiwalun
andauthored
Merge #419
419: Round up when calculating register size in bytes r=therealprof a=Tiwalun This fixes the issue in #418. Co-authored-by: Dominik Boehi <dominik.boehi@gmail.com>
2 parents 474dd00 + 566f7c7 commit 3033233

File tree

1 file changed

+2
-2
lines changed

1 file changed

+2
-2
lines changed

src/generate/peripheral.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -323,13 +323,13 @@ impl FieldRegions {
323323
let mut indices = Vec::new();
324324

325325
let field_start = field.offset;
326-
let field_end = field_start + field.size / BITS_PER_BYTE;
326+
let field_end = field_start + (field.size + BITS_PER_BYTE - 1) / BITS_PER_BYTE;
327327

328328
// The region that we're going to insert
329329
let mut new_region = Region {
330330
fields: vec![field.clone()],
331331
offset: field.offset,
332-
end: field.offset + field.size / BITS_PER_BYTE,
332+
end: field_end,
333333
ident: None,
334334
};
335335

0 commit comments

Comments
 (0)