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Fix downstream errors due to inline assembly #63

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16 changes: 16 additions & 0 deletions src/register/apsr.rs
Original file line number Diff line number Diff line change
Expand Up @@ -42,12 +42,28 @@ impl Apsr {
#[inline(always)]
pub fn read() -> Apsr {
let r: u32;

#[cfg(target_arch = "arm")]
unsafe {
asm!("mrs $0, APSR"
: "=r"(r)
:
:
: "volatile");
}

#[cfg(not(target_arch = "arm"))]
{ r = 0; }

Apsr { bits: r }
}


#[cfg(test)]
mod tests {
#[test]
fn it_should_compile() {
// Make sure that ARM-specific inline assembly is only included on ARM.
super::read();
}
}
22 changes: 20 additions & 2 deletions src/register/basepri.rs
Original file line number Diff line number Diff line change
Expand Up @@ -4,22 +4,40 @@
#[inline(always)]
pub fn read() -> u8 {
let r: u32;

#[cfg(target_arch = "arm")]
unsafe {
asm!("mrs $0, BASEPRI"
: "=r"(r)
:
:
: "volatile");
}

#[cfg(not(target_arch = "arm"))]
{ r = 0; }

r as u8
}

/// Writes to the CPU register
#[inline(always)]
pub unsafe fn write(basepri: u8) {
pub unsafe fn write(_basepri: u8) {
#[cfg(target_arch = "arm")]
asm!("msr BASEPRI, $0"
:
: "r"(basepri)
: "r"(_basepri)
: "memory"
: "volatile");
}


#[cfg(test)]
mod tests {
#[test]
fn it_should_compile() {
// Make sure that ARM-specific inline assembly is only included on ARM.
super::read();
unsafe { super::write(5); }
}
}
16 changes: 16 additions & 0 deletions src/register/control.rs
Original file line number Diff line number Diff line change
Expand Up @@ -107,12 +107,28 @@ impl Fpca {
#[inline(always)]
pub fn read() -> Control {
let r: u32;

#[cfg(target_arch = "arm")]
unsafe {
asm!("mrs $0, CONTROL"
: "=r"(r)
:
:
: "volatile");
}

#[cfg(not(target_arch = "arm"))]
{ r = 0; }

Control { bits: r }
}


#[cfg(test)]
mod tests {
#[test]
fn it_should_compile() {
// Make sure that ARM-specific inline assembly is only included on ARM.
super::read();
}
}
16 changes: 16 additions & 0 deletions src/register/faultmask.rs
Original file line number Diff line number Diff line change
Expand Up @@ -25,16 +25,32 @@ impl Faultmask {
#[inline(always)]
pub fn read() -> Faultmask {
let r: u32;

#[cfg(target_arch = "arm")]
unsafe {
asm!("mrs $0, FAULTMASK"
: "=r"(r)
:
:
: "volatile");
}

#[cfg(not(target_arch = "arm"))]
{ r = 0; }

if r & (1 << 0) == (1 << 0) {
Faultmask::Inactive
} else {
Faultmask::Active
}
}


#[cfg(test)]
mod tests {
#[test]
fn it_should_compile() {
// Make sure that ARM-specific inline assembly is only included on ARM.
super::read();
}
}
22 changes: 20 additions & 2 deletions src/register/lr.rs
Original file line number Diff line number Diff line change
Expand Up @@ -4,22 +4,40 @@
#[inline(always)]
pub fn read() -> u32 {
let r: u32;

#[cfg(target_arch = "arm")]
unsafe {
asm!("mov $0,R14"
: "=r"(r)
:
:
: "volatile");
}

#[cfg(not(target_arch = "arm"))]
{ r = 0; }

r
}

/// Writes `bits` to the CPU register
#[inline(always)]
pub unsafe fn write(bits: u32) {
pub unsafe fn write(_bits: u32) {
#[cfg(target_arch = "arm")]
asm!("mov R14,$0"
:
: "r"(bits)
: "r"(_bits)
:
: "volatile");
}


#[cfg(test)]
mod tests {
#[test]
fn it_should_compile() {
// Make sure that ARM-specific inline assembly is only included on ARM.
super::read();
unsafe { super::write(5); }
}
}
22 changes: 20 additions & 2 deletions src/register/msp.rs
Original file line number Diff line number Diff line change
Expand Up @@ -4,22 +4,40 @@
#[inline(always)]
pub fn read() -> u32 {
let r;

#[cfg(target_arch = "arm")]
unsafe {
asm!("mrs $0,MSP"
: "=r"(r)
:
:
: "volatile");
}

#[cfg(not(target_arch = "arm"))]
{ r = 0; }

r
}

/// Writes `bits` to the CPU register
#[inline(always)]
pub unsafe fn write(bits: u32) {
pub unsafe fn write(_bits: u32) {
#[cfg(target_arch = "arm")]
asm!("msr MSP,$0"
:
: "r"(bits)
: "r"(_bits)
:
: "volatile");
}


#[cfg(test)]
mod tests {
#[test]
fn it_should_compile() {
// Make sure that ARM-specific inline assembly is only included on ARM.
super::read();
unsafe { super::write(5); }
}
}
22 changes: 20 additions & 2 deletions src/register/pc.rs
Original file line number Diff line number Diff line change
Expand Up @@ -4,22 +4,40 @@
#[inline(always)]
pub fn read() -> u32 {
let r;

#[cfg(target_arch = "arm")]
unsafe {
asm!("mov $0,R15"
: "=r"(r)
:
:
: "volatile");
}

#[cfg(not(target_arch = "arm"))]
{ r = 0; }

r
}

/// Writes `bits` to the CPU register
#[inline(always)]
pub unsafe fn write(bits: u32) {
pub unsafe fn write(_bits: u32) {
#[cfg(target_arch = "arm")]
asm!("mov R15,$0"
:
: "r"(bits)
: "r"(_bits)
:
: "volatile");
}


#[cfg(test)]
mod tests {
#[test]
fn it_should_compile() {
// Make sure that ARM-specific inline assembly is only included on ARM.
super::read();
unsafe { super::write(5); }
}
}
16 changes: 16 additions & 0 deletions src/register/primask.rs
Original file line number Diff line number Diff line change
Expand Up @@ -25,16 +25,32 @@ impl Primask {
#[inline(always)]
pub fn read() -> Primask {
let r: u32;

#[cfg(target_arch = "arm")]
unsafe {
asm!("mrs $0, PRIMASK"
: "=r"(r)
:
:
: "volatile");
}

#[cfg(not(target_arch = "arm"))]
{ r = 0; }

if r & (1 << 0) == (1 << 0) {
Primask::Inactive
} else {
Primask::Active
}
}


#[cfg(test)]
mod tests {
#[test]
fn it_should_compile() {
// Make sure that ARM-specific inline assembly is only included on ARM.
super::read();
}
}
22 changes: 20 additions & 2 deletions src/register/psp.rs
Original file line number Diff line number Diff line change
Expand Up @@ -4,22 +4,40 @@
#[inline(always)]
pub fn read() -> u32 {
let r;

#[cfg(target_arch = "arm")]
unsafe {
asm!("mrs $0,PSP"
: "=r"(r)
:
:
: "volatile");
}

#[cfg(not(target_arch = "arm"))]
{ r = 0; }

r
}

/// Writes `bits` to the CPU register
#[inline(always)]
pub unsafe fn write(bits: u32) {
pub unsafe fn write(_bits: u32) {
#[cfg(target_arch = "arm")]
asm!("msr PSP,$0"
:
: "r"(bits)
: "r"(_bits)
:
: "volatile");
}


#[cfg(test)]
mod tests {
#[test]
fn it_should_compile() {
// Make sure that ARM-specific inline assembly is only included on ARM.
super::read();
unsafe { super::write(5); }
}
}