Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Expose configuration of the SEVONPEND bit within the System Control Register (SCR) #539

Merged
merged 1 commit into from
Jun 30, 2024
Merged

Expose configuration of the SEVONPEND bit within the System Control Register (SCR) #539

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
20 changes: 20 additions & 0 deletions cortex-m/src/peripheral/scb.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -832,6 +832,26 @@ impl SCB {
}
}

const SCB_SCR_SEVONPEND: u32 = 0x1 << 4;

impl SCB {
/// Set the SEVONPEND bit in the SCR register
#[inline]
pub fn set_sevonpend(&mut self) {
unsafe {
self.scr.modify(|scr| scr | SCB_SCR_SEVONPEND);
}
}

/// Clear the SEVONPEND bit in the SCR register
#[inline]
pub fn clear_sevonpend(&mut self) {
unsafe {
self.scr.modify(|scr| scr & !SCB_SCR_SEVONPEND);
}
}
}

const SCB_AIRCR_VECTKEY: u32 = 0x05FA << 16;
const SCB_AIRCR_PRIGROUP_MASK: u32 = 0x7 << 8;
const SCB_AIRCR_SYSRESETREQ: u32 = 1 << 2;
Expand Down
Loading