add Armv5te default start routine

[robamu]

I tested this with an ARM926EJ-S based board. Have not done much more than an empty main loop though, but that worked.

[jonathanpallant]

The versatileab machine in QEMU can be booted with an ARM926 processor (in fact, that's the normal processor - booting it with Cortex-R5 instead is a bit weird).

So, would you like to expand the versatileab examples to test this target?

[jonathanpallant]

As this is basically exactly the same as the v7-r start-up code, maybe we should just add arm_architecture="v5te" to that block of code?

[jonathanpallant]

FYI:

• The ARM9EJ-S TRM is at https://developer.arm.com/documentation/ddi0222/b?lang=en
• The Arm Architecture Reference Manual where v5TE was added is at https://www.intel.com/programmable/technical-pdfs/654202.pdf

[jonathanpallant]

So, I looked into this and there are some issues with the ARMv5TE target:

• in debug mode, the linker emits calls to intrinsics like __sync_val_compare_and_swap_4 (but they are optimised out in release mode) when doing ordinary atomic loads and stores (not compare-and-swaps). I don't know why.
• Our assembly-language handlers use SRSFD and RFEFD to push and pop the processor status register onto a specific stack (we have different stacks for each handler). However those instructions were added in ARMv7 and are not available in ARMv5TE or ARMv6. Therefore the assembly-language handler trampolines need to be re-written.

[robamu]

Oh, interesting.

I have the following interrupt handler from some C/C++ project

//------------------------------------------------------------------------------
/// Handles incoming interrupt requests by branching to the corresponding
/// handler, as defined in the AIC. Supports interrupt nesting.
//------------------------------------------------------------------------------
irqHandler:

/* Save interrupt context on the stack to allow nesting */
	sub     lr, lr, #4
	stmfd   sp!, {lr}
	mrs     lr, SPSR
	stmfd   sp!, {r0, lr}

/* Write in the IVR to support Protect Mode */
	ldr     lr, =AT91C_BASE_AIC
	ldr     r0, [lr, #AIC_IVR]
	str     lr, [lr, #AIC_IVR]

/* Branch to interrupt handler in Supervisor mode */
	msr     CPSR_c, #ARM_MODE_SVC
	stmfd   sp!, {r1-r3, r4, r12, lr}
	blx     r0
        
/* Restore scratch/used registers and LR from User Stack */
/* Disable Interrupt and switch back in IRQ mode */      
	ldmia   sp!, {r1-r3, r4, r12, lr}
	msr     CPSR_c, #ARM_MODE_IRQ | I_BIT

/* Acknowledge interrupt */
	ldr     lr, =AT91C_BASE_AIC
	str     lr, [lr, #AIC_EOICR]

/* Restore interrupt context and branch back to calling code */
	ldmia   sp!, {r0, lr}
	msr     SPSR_cxsf, lr
	ldmia   sp!, {pc}^

some of the handling probably belongs in a C handler, but the context code might be interesting..

[jonathanpallant]

That's broadly what I did: https://github.com/thejpster/cortex-ar/blob/416e1d61d39698a1480c54297002f02b9aa26981/aarch32-rt/src/arch_v4/undefined.rs#L19-L21

[thejpster]

I propose we close this and I'll come back with a fuller PR that resolves the architecture issues with our current assembly code (perhaps #78, or perhaps I'll do it in smaller pieces because that got a bit big)

[robamu]

Yes, this can be closed