Draft: Add more registers, and MPU support #6
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This is based off my copy at https://github.com/ferrous-systems/cortex-r/, which you can visit for the pre-history. My only changes in moving to this repository were removing the Ferrocene build (because you don't have a key for it), and adding some QEMU based tests.
tee runs before rustc, so it might not be there
Comes with big scary warning sign though.
The values are taken from the Cortex-R52 Reference Manual. We only have basic reads/writes for the new ones - I haven't drilled down into the bitfields.
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I added a PMSAv8-32 EL1 MPU driver. In doing so I realised a bunch of registers were Armv8-R only, so I moved them. |
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Hmm, my unit tests aren't running because they are in a module that is hidden unless you are targeting an Armv8-R processor. |
thejpster
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Added support for Armv7-R MPUs. Similar, but different, to Armv8-R MPUs. |
Allows me to drop the decode function.
thejpster
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The PMSAv8 support was tested on real hardware and works great. |
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I added a Generic Timer driver, and tested in on QEMU's Cortex-R52 machine. I'm not aware of a Armv7-R processor that has the Generic Timer, but there are some Armv7-A processors that do. |
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I had to change the generic_timer example so it would build for Armv7-R, because building the workspace builds everything, including all the examples. I'm not sure there's a way to have target-specific examples, sadly. |
It just stubs out all the timer code.
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The unit test code needs to see all the modules.
Updates #4 to add a bunch more registers.
I didn't do this with a macro to allow us to special-case each register in future, as demand requires.