More regs

src/registers.rs

@@ -37,6 +37,7 @@ mod fp;
 mod hcr_el2;
 mod id_aa64mmfr0_el1;
 mod id_aa64isar0_el1;
+mod id_aa64mmfr1_el1;
 mod id_aa64mmfr2_el1;
 mod lr;
 mod mair_el1;
@@ -65,6 +66,8 @@ mod ttbr0_el2;
 mod ttbr1_el1;
 mod vbar_el1;
 mod vbar_el2;
+mod vtcr_el2;
+mod vttbr_el2;
 
 pub use actlr_el1::ACTLR_EL1;
 pub use actlr_el2::ACTLR_EL2;
@@ -97,6 +100,7 @@ pub use fp::FP;
 pub use hcr_el2::HCR_EL2;
 pub use id_aa64mmfr0_el1::ID_AA64MMFR0_EL1;
 pub use id_aa64isar0_el1::ID_AA64ISAR0_EL1;
+pub use id_aa64mmfr1_el1::ID_AA64MMFR1_EL1;
 pub use id_aa64mmfr2_el1::ID_AA64MMFR2_EL1;
 pub use lr::LR;
 pub use mair_el1::MAIR_EL1;
@@ -125,3 +129,5 @@ pub use ttbr0_el2::TTBR0_EL2;
 pub use ttbr1_el1::TTBR1_EL1;
 pub use vbar_el1::VBAR_EL1;
 pub use vbar_el2::VBAR_EL2;
+pub use vtcr_el2::VTCR_EL2;
+pub use vttbr_el2::VTTBR_EL2;

src/registers/hcr_el2.rs

@@ -19,6 +19,15 @@ use tock_registers::{
 
 register_bitfields! {u64,
     pub HCR_EL2 [
+        /// When FEAT_S2FWB is implemented Forced Write-back changes the combined cachability of stage1
+        /// and stage2 attributes
+        FWB OFFSET(46) NUMBITS(1) [
+           /// Stage2 memory type and cacheability attributes are in bits[5:2] of the stage2 PTE
+           Disabled = 0,
+           /// Stage1 memory type can be overridden by Stage2 descriptor
+           Enabled = 1,
+        ],
+
         /// Controls the use of instructions related to Pointer Authentication:
         ///
         ///   - In EL0, when HCR_EL2.TGE==0 or HCR_EL2.E2H==0, and the associated SCTLR_EL1.En<N><M>==1.

src/registers/id_aa64mmfr1_el1.rs

@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2018-2022 by the author(s)
+//
+// Author(s):
+//   - Ali Saidi <alisaidi@amazon.com>
+
+//! AArch64 Memory Model Feature Register 1 - EL1
+//!
+//! Provides information about the implemented memory model and memory
+//! management support in AArch64 state.
+
+use tock_registers::{interfaces::Readable, register_bitfields};
+
+register_bitfields! {u64,
+    pub ID_AA64MMFR1_EL1 [
+        /// Support for configurable trapping delay of WFE instructions
+        TWED OFFSET(32) NUMBITS(4) [
+            /// Delaying the trapping of WFE instructions isn't supported
+            Unsupported = 0b0000,
+            /// Delaying the trapping of WFE instructions is supported
+            Supported = 0xb0001,
+        ],
+
+        /// Execute-never control at stage2 is distinct for EL0 and EL1
+        XNX OFFSET(28) NUMBITS(4) [
+            /// There are not distinct stage2 execute never controls for EL1 and EL0
+            Unsupported = 0b0000,
+            /// There are distinct stage2 execute never controls for EL1 and EL0
+            Supported = 0xb0001,
+        ],
+
+        /// Speculative reads can generate SError Interrupts
+        SpecSEI OFFSET(24) NUMBITS(4) [
+            /// PE never generates SError interrupts on a speculative read
+            Never = 0b0000,
+            /// PE may generate SError interrupts on a speculative read
+            Maybe = 0b0001
+        ],
+
+        /// Privileged Access Never support
+        PAN OFFSET(20) NUMBITS(4) [
+            /// Privileged Access Never isn't supported
+            Unsupported = 0b0000,
+            /// Privileged Access Never is supported
+            Supported = 0xb0001,
+            /// Privileged Access Never is supported along with AT instruction support
+            SupportedAT = 0xb0010,
+            /// Enhanced Privileged Access Never is supported
+            SupportedEPAN = 0xb0011,
+        ],
+
+        /// Limited Ordered regions support
+        LO OFFSET(16) NUMBITS(4) [
+            /// Limited Ordered regions aren't supported
+            Unsupported = 0b0000,
+            /// Limited Ordered regions are supported
+            Supported = 0xb0001,
+        ],
+
+        /// Hierarchical Permission can be disabled in TCRs
+        HPDS OFFSET(12) NUMBITS(4) [
+            /// HPDS aren't supported
+            Unsupported = 0b0000,
+            /// HPDS are supported
+            Supported = 0xb0001,
+        ],
+
+        /// Virtualization Host Extensions
+        VH OFFSET(8) NUMBITS(4) [
+            /// Virtualization Host Extensions aren't supported
+            Unsupported = 0b0000,
+            /// Virtualization Host Extensions are supported
+            Supported = 0xb0001,
+        ],
+
+        /// Number of VMID bits that are supported
+        VMIDBits OFFSET(4) NUMBITS(4) [
+            /// 8 bits of VMID are supported
+            Bits8 = 0b0000,
+            /// 16 bits of VMID are supported
+            Bits16 = 0b0010,
+        ],
+
+        /// Hardware updates to Access and Dirty flags in translation tables
+        HAFDBS OFFSET(0) NUMBITS(4) [
+            /// Not supported
+            Unsupported = 0b0000,
+            /// Access flag is supported
+            AccessOnly = 0xb0001,
+            /// Access and dirty flags are supported
+            AccessDirty = 0b0010,
+        ],
+    ]
+}
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = ID_AA64MMFR1_EL1::Register;
+
+    sys_coproc_read_raw!(u64, "ID_AA64MMFR1_EL1", "x");
+}
+
+pub const ID_AA64MMFR1_EL1: Reg = Reg;

src/registers/sctlr_el2.rs

@@ -27,6 +27,20 @@ register_bitfields! {u64,
             Big = 1
         ],
 
+        /// When FEAT_ExS is implemented control if taking an exception to EL2 is a context
+        /// synchonizing event
+        EIS OFFSET(22) NUMBITS(1) [
+            IsNotSynch = 0,
+            IsSynch = 1
+        ],
+
+        /// When FEAT_IESB is implemented control if an implict ESB is added at each exception
+        /// and before each ERET to/from EL2
+        IESB OFFSET(21) NUMBITS(1) [
+            Disable = 0,
+            Enable = 1
+        ],
+
         /// Force treatment of all memory regions with write permissions as XN.
         /// The possible values are:
         ///

src/registers/tcr_el1.rs

@@ -36,6 +36,20 @@ register_bitfields! {u64,
         ///     Reserved, RES0.
         TBID0  OFFSET(51) NUMBITS(1) [],
 
+        /// When FEAT_HAFDBS is implemented hardware can update the dirty flags in the stage1
+        /// descriptors
+        HD OFFSET(40) NUMBITS(1) [
+            Disable = 0,
+            Enable = 1,
+        ],
+
+        /// When FEAT_HAFDBS is implemented hardware can update the access flags in the stage1
+        /// descriptors
+        HA OFFSET(39) NUMBITS(1) [
+            Disable = 0,
+            Enable = 1,
+        ],
+
         /// Top Byte ignored - indicates whether the top byte of an address is used for address
         /// match for the TTBR1_EL1 region, or ignored and used for tagged addresses. Defined values
         /// are:

src/registers/tcr_el2.rs

@@ -18,6 +18,20 @@ use tock_registers::{
 register_bitfields! {u64,
     pub TCR_EL2 [
 
+        /// When FEAT_HAFDBS is implemented hardware can update the dirty flags in the stage1
+        /// descriptors
+        HD OFFSET(22) NUMBITS(1) [
+            Disable = 0,
+            Enable = 1,
+        ],
+
+        /// When FEAT_HAFDBS is implemented hardware can update the access flags in the stage1
+        /// descriptors
+        HA OFFSET(21) NUMBITS(1) [
+            Disable = 0,
+            Enable = 1,
+        ],
+
         /// Top Byte ignored - indicates whether the top byte of an address is used for address
         /// match for the TTBR0_EL2 region, or ignored and used for tagged addresses. Defined values
         /// are:

src/registers/vtcr_el2.rs

@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2018-2022 by the author(s)
+//
+// Author(s):
+//   - Ali Saidi <alisaidi@amazon.com>
+
+//! Virtualization Translation Control Register - EL2
+//!
+//! Provides control of stage2 translation of EL0/1
+
+use tock_registers::{
+    interfaces::{Readable, Writeable},
+    register_bitfields,
+};
+
+register_bitfields! {u64,
+    pub VTCR_EL2 [
+        /// Hardware dirty flag update in stage2 translations when EL2 is enabled
+        HD OFFSET(22) NUMBITS(1) [
+            /// Stage2 hardware management of dirty state disabled
+            Disabled = 0,
+            /// Stage2 hardware management of dirty state enabled
+            Enabled = 1,
+        ],
+        /// Hardware access flag update in stage2 translations when EL2 is enabled
+        HA OFFSET(21) NUMBITS(1) [
+            /// Stage2 hardware management of access state disabled
+            Disabled = 0,
+            /// Stage2 hardware management of access state enabled
+            Enabled = 1,
+        ],
+        /// VMID Size
+        VS OFFSET(19) NUMBITS(1) [
+            /// 8-bit VMID
+            Bits8 = 0,
+            /// 16-bit VMID
+            Bits16 = 1,
+        ],
+        /// Physical Address size of the second stage of translation
+        PS OFFSET(16) NUMBITS(3) [
+            /// 32 bits, 4GB
+            PA_32B_4GB = 0b000,
+            /// 36 bits, 64GB
+            PA_36B_64GB = 0b001,
+            /// 40 bits, 1TB
+            PA_40B_1TB = 0b010,
+            /// 42 bits, 4TB
+            PA_42B_4TB = 0b011,
+            /// 44 bits, 16TB
+            PA_44B_16TB = 0b100,
+            /// 48 bits, 256TB
+            PA_48B_256TB = 0b101,
+            /// 52 bits, 4PB
+            PA_52B_4PB = 0b110,
+        ],
+        /// Granule size used for `VTTBR_EL2`
+        TG0 OFFSET(14) NUMBITS(2) [
+            /// Granule size of 4KB
+            Granule4KB = 0b00,
+            /// Granule size of 16KB
+            Granule16KB = 0b10,
+            /// Granule size of 64KB
+            Granule64KB = 0b01,
+        ],
+        /// Shareability attribute for memory associated with translation table
+        /// walks using `VTTBR_EL2` and `VSTTBR_EL2`
+        SH0 OFFSET(12) NUMBITS(2) [
+            /// Non-shareable
+            Non = 0b00,
+            /// Outer sharable
+            Outer = 0b10,
+            /// Inner sharable
+            Inner = 0b11,
+        ],
+        /// Outer cacheability attribute for memory associated with translation table
+        /// walks using `VTTBR_EL2` and `VSTTBR_EL2`
+        ORGN0 OFFSET(10) NUMBITS(2) [
+            /// Normal non-cacheable memory
+            NormalNC = 0b00,
+            /// Normal Write-back, Read-allocate, Write-allocate
+            NormalWBRAWA = 0b01,
+            /// Normal Write-through, Read-allocate, no Write-allocate
+            NormalWTRAnWA = 0b10,
+            /// Normal Write-back, Read-allocate, no Write-allocate
+            NormalWBRAnWA = 0b11,
+        ],
+        /// Inner cacheability attribute for memory associated with translation table
+        /// walks using `VTTBR_EL2` and `VSTTBR_EL2`
+        IRGN0 OFFSET(8) NUMBITS(2) [
+            /// Normal non-cacheable memory
+            NormalNC = 0b00,
+            /// Normal Write-back, Read-allocate, Write-allocate
+            NormalWBRAWA = 0b01,
+            /// Normal Write-through, Read-allocate, no Write-allocate
+            NormalWTRAnWA = 0b10,
+            /// Normal Write-back, Read-allocate, no Write-allocate
+            NormalWBRAnWA = 0b11,
+        ],
+        /// Starting level of the stage2 translation lookup
+        SL0 OFFSET(6) NUMBITS(2) [],
+        /// The size of the offest of the memory region addressed by the `VTTBR_EL2`
+        T0SZ OFFSET(0) NUMBITS(6) [],
+
+    ]
+}
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = VTCR_EL2::Register;
+
+    sys_coproc_read_raw!(u64, "VTCR_EL2", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = VTCR_EL2::Register;
+
+    sys_coproc_write_raw!(u64, "VTCR_EL2", "x");
+}
+
+pub const VTCR_EL2: Reg = Reg {};
+

src/registers/vttbr_el2.rs

@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2018-2022 by the author(s)
+//
+// Author(s):
+//   - KarimAllah Ahmed <karahmed@amazon.com>
+//   - Andre Richter <andre.o.richter@gmail.com>
+
+use tock_registers::{
+    interfaces::{Readable, Writeable},
+    register_bitfields,
+};
+
+register_bitfields! {u64,
+    pub VTTBR_EL2 [
+        /// An VMID for the translation table
+        ///
+        /// If the implementation only supports 8-bit VM IDs the top 8 bits are RES0
+        VMID  OFFSET(48) NUMBITS(16) [],
+
+        /// Translation table base address
+        BADDR OFFSET(1) NUMBITS(48) [],
+
+        /// Common not Private
+        CnP   OFFSET(0) NUMBITS(1) []
+    ]
+}
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = VTTBR_EL2::Register;
+
+    sys_coproc_read_raw!(u64, "VTTBR_EL2", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = VTTBR_EL2::Register;
+
+    sys_coproc_write_raw!(u64, "VTTBR_EL2", "x");
+}
+
+impl Reg {
+    #[inline(always)]
+    pub fn get_baddr(&self) -> u64 {
+        self.read(VTTBR_EL2::BADDR) << 1
+    }
+
+    #[inline(always)]
+    pub fn set_baddr(&self, addr: u64) {
+        self.write(VTTBR_EL2::BADDR.val(addr >> 1));
+    }
+}
+
+pub const VTTBR_EL2: Reg = Reg {};