- 👋 Hi, I’m @russellfriesenhahn
- 👀 I’m interested in FOSS Hardware EDA tools, Digital Design, Verilog, ASICs, FPGAs, Python
- 🌱 I’m currently learning Python, OpenLane
- 📫 Reach me by leaving a message on this project.
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caravel_user_project
caravel_user_project PublicForked from efabless/caravel_user_project
https://caravel-user-project.readthedocs.io
Verilog
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stc0
stc0 PublicTest Chip 0 that implements an FFT butterfly and interfaces to stream data.
Verilog
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OpenSourcePhyDesign
OpenSourcePhyDesign PublicForked from patil19/OpenSourcePhyDesign
SOC Physical Design Workshop with Open Source Tools
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openlane
openlane PublicForked from The-OpenROAD-Project/OpenLane
OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
Verilog
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