RTL Design Engineer (in progress) | Verilog/SystemVerilog | FPGA
Microelectronics Student at UFRGS
CI Expert – Softex (RTL Design & Synthesis Track)
Synopsys
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UFRGS
- PORTO ALEGRE RIO GRANDE DO SUL
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09:40
(UTC -12:00) - www.linkedin.com/in/rcpanalistadedados
Popular repositories Loading
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rtl-synthesis-portfolio-
rtl-synthesis-portfolio- PublicRTL synthesis and front-end VLSI portfolio demonstrating timing-driven digital design, SDC constraints, and STA workflows for ASIC/SoC.
Tcl
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gemio-digital-chip
gemio-digital-chip PublicPlataforma de co-simulação HW/SW com SystemC e QEMU para validação pré-silicon
C++
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