This is a educational emulator I am building. The idea is that the emulator will help you understand how CPUs work from a conceptual level.
This emulator interprets the machine code for the RISC-V ISA (Instruction Set Architecture). RISC-V is a open source freely licensed ISA that formed out a research project at UC Berkeley, learn more at riscv.org.
This emulator targets the RV32i subset of the RISC-V ISA.
This is the base level 32-bit architecture without hardware support for things like floating point or single-cycle multiply.
In the future I might decide to add support for more instructions.
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Clone:
git clone https://github.com/rohbotics/rv_emulator.git -
Go into a build dir:
cd rv_emulator; mkdir build; cd build -
Run CMake:
cmake .. -
Build:
make -
Run tests (optional):
make check
All dependencies are vendored (git subtree into the external directory).