[128-bit] FPGA Implementation of an Asynchronous Quasi-Random Number Generator Using Linear-feedback Shift Registers and Mousetrap Logic

Please, Cite the Paper

R. N. Wuerdig, M. L. L. Sartori and N. L. V. Calazans, "Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT Variations," 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), Armenia, Colombia, 2019, pp. 137-140, doi: 10.1109/LASCAS.2019.8667561.)

About

LFSRs are well-known circuits for generating pseudo-random sequences. At every cycle of the clock, you have a different value. However, the circuit presented in this work uses an asynchronous implementation (clockless) to mask the cycle and decrease the predictability after a certain amount of time. The PVT variations in this circuit will cause a displacement in time of each code for the pseudo-sequence, so the worst is the ring (in terms of variability), the better it is in terms of it is randomness.

Goals

• Increase Entropy Through Time Displacement
• Fully Digital High Variability Number Generator

Fig. I - Mousetrap Asynchronous QRNG Architecture

Test-Bench
This circuit was prototyped on a Nexys board equipped with a Xilinx XC3S200 Spartan-3 FPGA.