Add RzIL implementation of MIPS32 ops

[wargio]

Your checklist for this pull request

• I've read the guidelines for contributing to this repository.
• I made sure to follow the project's coding style.
• I've documented every RZ_API function and struct this PR changes.
• I've added tests that prove my changes are effective (required for changes to RZ_API).
• I've updated the Rizin book with the relevant information (if needed).

Detailed description

Adds RzIL uplifting for capstone mips.

• Implemented all 75 common ops from MIPS32 spec
• Implemented 7 common ops from MIPS64 spec (lwu, ld, dadd, etc...)
• Implemented 35 special ops (interrupts, cache sync, cache prefetch, TLB, breakpoints, traps, etc..) as NOP
• Ignored most of the 58 floating point ops from MIPS32 spec (will be done in another PR)
• Ignored 20 Hardware ops (syscall, interrupt return, etc..) from MIPS32 spec (will be done in another PR)

Test plan

Add emulateme binaries.

[wargio]

I am thinking to add a sha1 emulateme binary which will add more operations to check the correctness of the execution

[notxvilka]

Could you please provide a coverage? How many instructions are implemented and how many - aren't? Floating point aside, I see there are many still aren't implemented, judging by the source code. Or at least explain what is implemented and what currently isn't in the PR description.

[Rot127]

Just those little things.
Please run the asm tests with ASAN and the leak sanitizer, if not done yet.

[wargio]

Please run the asm tests with ASAN and the leak sanitizer, if not done yet.

Already done. no changes.

[notxvilka]

LGTM once you address @Rot127 feedback.