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prefix comparision instructions with vm(#160) #181
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The destination of Integer/FP comparison instructions is mask register, so modify related instructions with vm prefixed. Signed-off-by: Weiwei Wang <weiwei.wangx@outlook.com>
aswaterman
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May 20, 2019
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Thanks, @wwang0. Looks good to me, but will wait for @kasanovic to click the merge button.
Add missing vs2 in vid.v example Signed-off-by: Weiwei Wang <weiwei.wangx@outlook.com>
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There is no vs2 operand to the vid.v instruction, so this change is incorrect. |
chihminchao
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Jun 7, 2019
add 'm' prefix since the destination is mask register
ref:
riscvarchive/riscv-v-spec#181
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
chihminchao
added a commit
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Jun 14, 2019
add 'm' prefix since the destination is mask register
ref:
riscvarchive/riscv-v-spec#181
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
aswaterman
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Jun 19, 2019
* rvv: fault-first also support segement
based on 7.8.1, add missing segment supoort for fault first load
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
* rvv: comparision instructions has 'm' prefix
add 'm' prefix since the destination is mask register
ref:
riscvarchive/riscv-v-spec#181
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
* rvv: reserved vid.v operand
follow v0.7.1 change
ref:
riscvarchive/riscv-v-spec#160
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
* rvv: add vfrsub.vf
follow v-spec 0.7.1
ref:
riscvarchive/riscv-v-spec@65d2e23
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
* rvv: add amo encoding table
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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The destination of Integer/FP comparison instructions is mask
register, so modify related instructions with vm prefixed.
Signed-off-by: Weiwei Wang weiwei.wangx@outlook.com