Add changes from #918.

riscv · Jan 26, 2024 · d3b3f76 · d3b3f76
1 parent 5467850
commit d3b3f76
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/Sdtrig.adoc b/Sdtrig.adoc
@@ -308,7 +308,8 @@ been executed once.
 === Trigger Module Registers
 
 These registers are CSRs, accessible using the RISC-V `csr` opcodes and
-optionally also using abstract debug commands.
+optionally also using abstract debug commands. They are the only mechanism
+to access the triggers.
 
 Almost all trigger functionality is optional. All `tdata` registers
 follow write-any-read-legal semantics. If a debugger writes an