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Vector AES Mock SAIL code. #24
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- Added some mock functions for vector extension register access and constant access. - Get/Set elements of 128 bits - Get number of elements to work on. - See #24, #26 On branch dev/next-release Your branch is ahead of 'origin/dev/next-release' by 4 commits. (use "git push" to publish your local commits) Changes to be committed: modified: sail/riscv_types_crypto.sail Changes not staged for commit: modified: bin/parse_opcodes.py modified: extern/riscv-gnu-toolchain (modified content) modified: extern/riscv-isa-sim (modified content) Untracked files: sail/riscv_insts_crypto_rvv_aes.sail sail/riscv_insts_crypto_rvv_alu.sail sail/riscv_insts_crypto_rvv_sha.sail
- See #25, #24 - Boilerplate for all vector AES instrucitons. - Mock code for single round AES instructions. On branch dev/next-release Your branch is ahead of 'origin/dev/next-release' by 8 commits. (use "git push" to publish your local commits) Changes to be committed: new file: sail/riscv_insts_crypto_rvv_aes.sail Changes not staged for commit: modified: extern/riscv-gnu-toolchain (modified content) modified: extern/riscv-isa-sim (modified content)
- See #24 On branch dev/next-release Your branch is up-to-date with 'origin/dev/next-release'. Changes to be committed: modified: sail/riscv_crypto_tests.sail modified: sail/riscv_insts_crypto_rvv_aes.sail modified: sail/riscv_types_crypto.sail Changes not staged for commit: modified: extern/riscv-gnu-toolchain (modified content) modified: extern/riscv-isa-sim (modified content)
- Tests for key schedule step: AES128/256 - Tests for single round encrypt. - Tests for round transformations. - Tests for getting last round keys from initial cipher key: AES 128/256 - Implement get last round key: AES 128/256 On branch dev/next-release Your branch is up-to-date with 'origin/dev/next-release'. Changes to be committed: modified: sail/riscv_crypto_tests.sail modified: sail/riscv_insts_crypto_rvv_aes.sail modified: sail/riscv_types_crypto.sail Changes not staged for commit: modified: extern/riscv-gnu-toolchain (modified content) modified: extern/riscv-isa-sim (modified content)
Hey @ben-marshall, this seems interesting and I would like to take up on it. I have experience with AES and DES implementations in Verilog and quite familiar with RISCV ISA. Where do I start for the SAIL model? |
Until the Sail model for RISC-V Vector is complete, we cannot add in modifications to SAIL needed for Vector Crypto. Instead, the specification will continue to use SAIL-like code in the fashion that Ben had created. |
Write mocked SAIL descriptions of the vector AES instructions. Because there is no support for the base vector extension, these functions assume that extraction of input elements from the vector registers is a solved problem and that they are just passed in as arguments. The mocked functions just return the result for a single set of elements. They do not change any architectural state.
AES 128 Single Round:
AES 128 All Round:
AES 256 Single Round:
AES 256 All Round:
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