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v-spec 0.7.1 support #303

Merged
merged 17 commits into from
Jun 18, 2019
Merged

v-spec 0.7.1 support #303

merged 17 commits into from
Jun 18, 2019

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chihminchao
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Based on 0.7.1

The implementation supports
by arch

  • RV32 and RV64
  • Vector register length (VLEN): 32 bits to 4096 bits, power by 2 (doesn’t test more than 4096 bits)
  • Vector element length (ELEN): 32 bits to VLEN, power by 2
  • Vector strip length(SLEN): 32 bits to 512 bits, power by 2 (doesn’t test more than 512 bits)

by instruction category

  • integer/fixed-point/mask/reduction/permutation
    sections: 12/13/15.1 ~ 15.2/16/17
    element size: 8/16/32/64
    support ediv: 1
  • load/store
    section: 7
    element size: 8/16/32/64
  • floating-point
    sections: 14/15.3 ~ 15.4
    element size: 32

@chihminchao
build: build softfloat with pic and provide shared library
df54c7a 
vector unit tests need identical floating library to generate golden
pattern

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@chihminchao
rvv: re-arrange instruction list by different extension
25607e2 
It is preparatory commit for vector extension.
v-ext has hundresds of new instructions and mixing them with scalar instructions
messes up code.

Separate each extension into different list to make thing clean

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@aswaterman aswaterman self-requested a review June 11, 2019 08:35
@aswaterman
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Cool. Will review and provide feedback over the next day or so.

aswaterman
aswaterman reviewed Jun 11, 2019
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aswaterman reviewed Jun 11, 2019
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@aswaterman
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Okay. We can fix this later if people complain. Can you update the autoconf/configure scripts to check for a 64-bit host, and issue a useful error message if the host is 32-bit?

@myftptoyman
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How to test these vector instructions ? Current assembler can't compile vector instructions

@aswaterman
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aswaterman commented Jun 13, 2019 via email

@jim-wilson
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You can find rvv 0.7.1 binutils sources in the rvv branch at
github.com/sifive/riscv-binutils-gdb
These have been publicly visible for a few months, though they haven't been "stable" until now. Pass -march=rv64gcv or similar to the assembler to enable vector instruction support.

We should create a branch in riscv/riscv-gnu-toolchain to hold this, and some minimal gcc patches to support the vector extension, but I'm swamped with work and haven't gotten around to it yet. Plus I wasn't sure what exactly was happening with the spike work.

There is an existing rvv branch in riscv/riscv-gnu-toolchain, but it holds rvv 0.6 support. I don't know if that is useful to anyone anymore, so I don't know if it is safe to overwrite that or not. I could alternatively create a rvv-0.7 branch for the new work to avoid conflicting with the old work and avoid conflicts with possible future work.

I'd rather not have non-upstream patches on riscv-gnu-toolchain master, and I'd rather not upstream patches that aren't an official standard yet, so I don't have any better suggestion than creating an rvv specific branch.

@chihminchao
rvv: add the v-spec-0.7.1 encoding
f28875b 
also remove duplicated one in fesvr

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@chihminchao
disams: make instruction name dynamic
e79b092 
It is a preparatory commit.
vector extension has supported segment load/store which have
the same prefix and a serial number as suffix.
ex:
  base :
    vlsegb.v
  variation:
    vlseg2.v, vlseg3b ... vlseg8b

dynamic string can reduce the typing effort

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@chihminchao
rvv: disasm: add v-spec 0.7.1 support
3d7c842 
support most of vector instruction except for AMO extension

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@chihminchao
rvv: add configuration and command-line option
004649e 
1. configure option "--with-varch"
the option defines the default u-arch implementatiton-decided parameter

  VLEN:  vector register length in bit
  SLEN:  striping distance in bit
  ELEN:  max element size in bit

  ex: --with-vector=v128:e32:s128

2. add __int128_t type checking

3. add --varch command option and help message

  ex: --varch=v512:e64:s512

Signed-off-by: Dave Wen <dave.wen@sifive.com>
@chihminchao
rvv: add vector unit structure
9de0cdd 
Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
@chihminchao
rvv: add varch option parser and initialize vector unit
48fe0c4 
the default vector parameters are defined in configuration time but can
be changed throught command-line option

Signed-off-by: Dave Wen <dave.wen@sifive.com>
@chihminchao
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Changes

  1. separate vfunary0/vfunary1
  2. check 128 bit integer support in autoconf
  3. rollback vector control register change
  4. remove some unused define
  5. remove register change feature in interactive mode

@aswaterman
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Thank you for addressing all these requests! I think it is @palmer-dabbelt's turn to review the code.

@myftptoyman
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I have builld success the rvv Spike and binutils rvv 0.7.1 and run on gcc inline assembly. It is look very good. I will try some algorithm on this platform. Thank you.

palmer-dabbelt
palmer-dabbelt previously approved these changes Jun 16, 2019
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@palmer-dabbelt palmer-dabbelt dismissed their stale review June 16, 2019 07:15

I don't understand the github interface

palmer-dabbelt
palmer-dabbelt approved these changes Jun 16, 2019
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riscv/decode.h
}else if(sew == e64){ \
VV_PARAMS(e64); \
BODY; \
} \
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This should fail on an unknown SEW. There's a bunch of these.

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we're checking the unsupported SEW at very begging of each instruction. Please reference the decode.h:460.

riscv/interactive.cc Outdated Show resolved Hide resolved
@chihminchao
rvv: extend interactive debug
887dbf2 
add command to show vector register in debug mode

Signed-off-by: Bruce Hoult <bruce@hoult.org>
@chihminchao
rvv: extend softfloat to support 16-64 min/max function
b96463c 
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@chihminchao
rvv: add saturation helper function
371e3fe 
1. add integer signed add/subu and unsigend add/sub saturation function
2. merge these with mulhi helper

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@chihminchao
rvv: add control instructions and system register access
235aa58 
Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@chihminchao
rvv: add integer/fixed-point/mask/reduction/permutation instructions
655aedc 
based on v-spec 0.7.1, support
  sections: 12/13/15.1 ~ 15.2/16/17
  element size: 8/16/32/64
  support ediv: 1

Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
@chihminchao
rvv: add load/store instructions
80ebc70 
based on v-spec 0.7.1, support
  section: 7
  element size: 8/16/32/64

Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
Signed-off-by: Zakk Chen <zakk.chen@sifive.com>
@chihminchao
rvv: add floating-point instructions
833b965 
based on v-spec 0.7.1, support
  sections: 14/15.3 ~ 15.4
  element size: 32

Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
@chihminchao
rvv: add simple instruction parsing tool
77adcb1 
the tool can parse the instruction name from spike debug log to help
dsp kernel designer check what instructions have been used

Signed-off-by: Jerry Shih <bignose1007@gmail.com>
@chihminchao
rvv: describe the supported vector spec version
92e0056 
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
@chihminchao
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Changes:

  1. fix vext signed extension issue
  2. refine register checking
  3. add register overlapping checking for vslide1up and vslideup
  4. follow review's suggestion to refine register dump function.

@aswaterman
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I think this version of the patch is mergeable; any objections?

@palmer-dabbelt
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palmer-dabbelt commented Jun 18, 2019 via email

@aswaterman
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Thanks @chihminchao!

@aswaterman aswaterman merged commit 49eb5a5 into riscv-software-src:master Jun 18, 2019
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@kito-cheng kito-cheng kito-cheng left review comments

@palmer-dabbelt palmer-dabbelt palmer-dabbelt approved these changes

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7 participants
@chihminchao @aswaterman @myftptoyman @jim-wilson @palmer-dabbelt @davetw @kito-cheng