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Description
Technical Group
Privileged Spec IC
ratification-pkg
Priv 1.13
Technical Liaison
Greg Favor
Task Category
SAIL model
Task Sub Category
- gcc
- binutils
- gdb
- intrinsics
- Java
- KVM
- ld
- llvm
- Linux kernel
- QEMU
- Spike
Ratification Target
3Q2024
Statement of Work (SOW)
Component names:
Requirements:
Provide Sail model function for the following Priv 1.13 updates:
- Defined the misa.V field to reflect that the V extension has been implemented.
- Exposed count-overflow interrupts to VS-mode.
- Redefined misa.MXL to be read-only, making MXLEN a constant.
- Added the constraint that SXLEN≥UXLEN.
- Defined the RV32-only medelegh and hedelegh CSRs. (1)
- Allocated interrupt 13 for Sscofpmf LCOFI interrupt. (2)
The following footnotes clarify level of support:
- Limitations in the hypervisor support will determine how much function can be enabled.
- Limitations in the counter support will determine how much function can be enabled.
Note: the following features of Priv 1.13 require ACT infrastructure that prevent their implementation at this time:
- Defined hardware error and software check exception codes.
- Defined the misaligned atomicity granule PMA, superseding the proposed Zam extension.
Deliverables:
- Accepted Sail model updates (PRs) in support of the above Priv 1.13 features
- Accepted Sail build verification tests (PRs) to support the new model features
Acceptance Criteria:
- Passing of the ACT tests (regression)
- Passing of the build verification tests for Priv 1.13 (Note: the ACT tests for Priv 1.13 are requested to be self-checking and as such should be usable as BVTs. See #43 for more discussion.)
Projected timeframe: (best guess date)
2 person months (part time)
SOW Signoffs: (delete those not needed)
- Task group liaison sign-off
- Development partner sign-off
- Golden Model SIG sign-off (if SAIL work)
Waiver
- Freeze
- Ratification
Pull Request Details
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