Sg2042 v1.8

firmware/fw_base.S

@@ -349,7 +349,7 @@ _start_warm:
 	add	a4, a4, 1
 	blt	a4, s7, 1b
 2:	add	s6, a4, zero
-3:	bge	s6, s7, _start_hang
+3:	bgeu	s6, s7, _start_hang
 
 	/* Find the scratch space based on HART index */
 	lla	tp, _fw_end
@@ -647,6 +647,8 @@ memcmp:
 	.align 3
 	.globl _trap_handler
 _trap_handler:
+	sfence.vma	zero, t0
+
 	TRAP_SAVE_AND_SETUP_SP_T0
 
 	TRAP_SAVE_MEPC_MSTATUS 0

include/sbi/riscv_barrier.h

@@ -25,19 +25,19 @@
 #define mb()			RISCV_FENCE(iorw,iorw)
 
 /* Read Memory barrier */
-#define rmb()			RISCV_FENCE(ir,ir)
+#define rmb()			RISCV_FENCE(ir,iorw)
 
 /* Write Memory barrier */
-#define wmb()			RISCV_FENCE(ow,ow)
+#define wmb()			RISCV_FENCE(iorw,ow)
 
 /* SMP Read & Write Memory barrier */
 #define smp_mb()		RISCV_FENCE(rw,rw)
 
 /* SMP Read Memory barrier */
-#define smp_rmb()		RISCV_FENCE(r,r)
+#define smp_rmb()		RISCV_FENCE(r,rw)
 
 /* SMP Write Memory barrier */
-#define smp_wmb()		RISCV_FENCE(w,w)
+#define smp_wmb()		RISCV_FENCE(rw,w)
 
 /* CPU relax for busy loop */
 #define cpu_relax()						\
@@ -48,11 +48,20 @@ do {								\
 
 /* clang-format on */
 
+#ifdef CONFIG_PLATFORM_SOPHGO_MANGO
+ #define __smp_store_release(p, v)   \
+ 	do {                        \
+ 		RISCV_FENCE(rw, w); \
+ 		*(p) = (v);         \
+		RISCV_FENCE(w, rw); \
+ 	} while (0)
+#else
 #define __smp_store_release(p, v)   \
 	do {                        \
 		RISCV_FENCE(rw, w); \
 		*(p) = (v);         \
 	} while (0)
+#endif
 
 #define __smp_load_acquire(p)            \
 	({                               \

include/sbi/riscv_encoding.h

@@ -732,6 +732,8 @@
 /* Counter Overflow CSR */
 #define CSR_SCOUNTOVF			0xda0
 
+#define MCOUNTEREN_TM			(_UL(1) << 1)
+
 /* Debug/Trace Registers */
 #define CSR_TSELECT			0x7a0
 #define CSR_TDATA1			0x7a1

include/sbi/sbi_platform.h

@@ -56,6 +56,7 @@ struct sbi_domain_memregion;
 struct sbi_ecall_return;
 struct sbi_trap_regs;
 struct sbi_hart_features;
+struct sbi_tlb_info;
 union sbi_ldst_data;
 
 /** Possible feature flags of a platform */
@@ -76,6 +77,9 @@ struct sbi_platform_operations {
 	/* Check if specified HART is allowed to do cold boot */
 	bool (*cold_boot_allowed)(u32 hartid);
 
+	/* Check if platform force emulate time csr, instead of using csr directly */
+	bool (*force_emulate_time_csr)(void);
+
 	/* Check if platform requires single firmware region */
 	bool (*single_fw_region)(void);
 
@@ -125,6 +129,20 @@ struct sbi_platform_operations {
 	/** Get tlb fifo num entries*/
 	u32 (*get_tlb_num_entries)(void);
 
+	void (*local_fence_i)(struct sbi_tlb_info *tinfo);
+
+	void (*local_sfence_vma)(struct sbi_tlb_info *tinfo);
+
+	void (*local_sfence_vma_asid)(struct sbi_tlb_info *tinfo);
+
+	void (*local_hfence_gvma_vmid)(struct sbi_tlb_info *tinfo);
+
+	void (*local_hfence_gvma)(struct sbi_tlb_info *tinfo);
+
+	void (*local_hfence_vvma_asid)(struct sbi_tlb_info *tinfo);
+
+	void (*local_hfence_vvma)(struct sbi_tlb_info *tinfo);
+
 	/** Initialize platform timer during cold boot */
 	int (*timer_init)(void);
 
@@ -305,6 +323,81 @@ static inline u32 sbi_platform_tlb_fifo_num_entries(const struct sbi_platform *p
 	return sbi_hart_count();
 }
 
+static inline u32 sbi_platform_local_fence_i(
+					const struct sbi_platform *plat,
+					struct sbi_tlb_info *tinfo)
+{
+	if (plat && sbi_platform_ops(plat)->local_fence_i) {
+		sbi_platform_ops(plat)->local_fence_i(tinfo);
+		return 0;
+	}
+	return SBI_ENOTSUPP;
+}
+
+static inline u32 sbi_platform_local_sfence_vma(
+					const struct sbi_platform *plat,
+					struct sbi_tlb_info *tinfo)
+{
+	if (plat && sbi_platform_ops(plat)->local_sfence_vma) {
+		sbi_platform_ops(plat)->local_sfence_vma(tinfo);
+		return 0;
+	}
+	return SBI_ENOTSUPP;
+}
+
+static inline u32 sbi_platform_local_sfence_vma_asid(
+					const struct sbi_platform *plat,
+					struct sbi_tlb_info *tinfo)
+{
+	if (plat && sbi_platform_ops(plat)->local_sfence_vma_asid) {
+		sbi_platform_ops(plat)->local_sfence_vma_asid(tinfo);
+		return 0;
+	}
+	return SBI_ENOTSUPP;
+}
+
+static inline u32 sbi_platform_local_hfence_gvma_vmid(
+					const struct sbi_platform *plat,
+					struct sbi_tlb_info *tinfo)
+{
+	if (plat && sbi_platform_ops(plat)->local_hfence_gvma_vmid) {
+		sbi_platform_ops(plat)->local_hfence_gvma_vmid(tinfo);
+		return 0;
+	}
+	return SBI_ENOTSUPP;
+}
+
+static inline u32 sbi_platform_local_hfence_gvma(
+					const struct sbi_platform *plat,
+					struct sbi_tlb_info *tinfo)
+{
+	if (plat && sbi_platform_ops(plat)->local_hfence_gvma) {
+		sbi_platform_ops(plat)->local_hfence_gvma(tinfo);
+		return 0;
+	}
+	return SBI_ENOTSUPP;
+}
+static inline u32 sbi_platform_local_hfence_vvma_asid(
+					const struct sbi_platform *plat,
+					struct sbi_tlb_info *tinfo)
+{
+	if (plat && sbi_platform_ops(plat)->local_hfence_vvma_asid) {
+		sbi_platform_ops(plat)->local_hfence_vvma_asid(tinfo);
+		return 0;
+	}
+	return SBI_ENOTSUPP;
+}
+static inline u32 sbi_platform_local_hfence_vvma(
+					const struct sbi_platform *plat,
+					struct sbi_tlb_info *tinfo)
+{
+	if (plat && sbi_platform_ops(plat)->local_hfence_vvma) {
+		sbi_platform_ops(plat)->local_hfence_vvma(tinfo);
+		return 0;
+	}
+	return SBI_ENOTSUPP;
+}
+
 /**
  * Get total number of HARTs supported by the platform
  *
@@ -350,6 +443,20 @@ static inline bool sbi_platform_cold_boot_allowed(
 	return true;
 }
 
+/**
+ * Check whether given platform should force emulate time CSR
+ *
+ * @param plat pointer to struct sbi_platform
+ *
+ * @return true such platform force emulate time CSR, false otherwise
+ */
+static inline bool sbi_platform_force_emulate_time_csr(const struct sbi_platform *plat)
+{
+	if (plat && sbi_platform_ops(plat)->force_emulate_time_csr)
+		return sbi_platform_ops(plat)->force_emulate_time_csr();
+	return false;
+}
+
 /**
  * Check whether platform requires single firmware region
  *

include/sbi_utils/timer/aclint_mtimer.h

@@ -35,6 +35,7 @@ struct aclint_mtimer_data {
 	u32 hart_count;
 	bool has_64bit_mmio;
 	bool has_shared_mtime;
+	bool use_extern_domain;
 	/* Private details (initialized and used by ACLINT MTIMER library) */
 	struct aclint_mtimer_data *time_delta_reference;
 	unsigned long time_delta_computed;

include/sbi_utils/timer/sg2042_gmt.h

@@ -0,0 +1,21 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2025 SOPHGO Corporation
+ *
+ * Authors:
+ *   Chao Wei <chao.wei@sophgo.com>
+ */
+
+#ifndef __SG2042_GMT_H__
+#define __SG2042_GMT_H__
+
+int sg2042gmt_cold_timer_init(unsigned long mtimer_base,
+			      unsigned long mtimecmp_base,
+			      unsigned long mtimecmp_size,
+			      unsigned long delcared_freq,
+			      unsigned long actual_freq,
+			      unsigned long timecmp_freq);
+int sg2042gmt_warm_timer_init(void);
+
+#endif /* __SG2042_GMT_H__ */

lib/sbi/riscv_locks.c

@@ -64,6 +64,8 @@ void spin_lock(spinlock_t *lock)
 #error "need A or Zaamo or Zalrsc"
 #endif
 
+		"fence w, o\n"
+
 		/* Did we get the lock? */
 		"	srli	%1, %0, %6\n"
 		"	and	%1, %1, %5\n"
@@ -83,4 +85,5 @@ void spin_lock(spinlock_t *lock)
 void spin_unlock(spinlock_t *lock)
 {
 	__smp_store_release(&lock->owner, lock->owner + 1);
+	RISCV_FENCE(w, o);
 }

lib/sbi/sbi_hart.c

@@ -60,6 +60,11 @@ static void mstatus_init(struct sbi_scratch *scratch)
 	if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_10)
 		csr_write(CSR_MCOUNTEREN, -1);
 
+	if (sbi_platform_force_emulate_time_csr(sbi_platform_thishart_ptr())) {
+		csr_clear(CSR_MCOUNTEREN, MCOUNTEREN_TM);
+		csr_clear(CSR_SCOUNTEREN, MCOUNTEREN_TM);
+	}
+
 	/* All programmable counters will start running at runtime after S-mode request */
 	if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_11)
 		csr_write(CSR_MCOUNTINHIBIT, 0xFFFFFFF8);
@@ -670,7 +675,8 @@ static int hart_detect_features(struct sbi_scratch *scratch)
 		__set_bit(__csr_id, hfeatures->csrs);
 
 	__check_csr_existence(CSR_CYCLE, SBI_HART_CSR_CYCLE);
-	__check_csr_existence(CSR_TIME, SBI_HART_CSR_TIME);
+	if (!sbi_platform_force_emulate_time_csr(sbi_platform_thishart_ptr()))
+		__check_csr_existence(CSR_TIME, SBI_HART_CSR_TIME);
 	__check_csr_existence(CSR_INSTRET, SBI_HART_CSR_INSTRET);
 
 #undef __check_csr_existence

lib/sbi/sbi_init.c

@@ -216,6 +216,7 @@ static void wake_coldboot_harts(struct sbi_scratch *scratch)
 {
 	/* Mark coldboot done */
 	__smp_store_release(&coldboot_done, 1);
+	RISCV_FENCE(w, o);
 }
 
 static unsigned long entry_count_offset;

lib/sbi/sbi_pmu.c

@@ -689,6 +689,8 @@ int sbi_pmu_ctr_stop(unsigned long cbase, unsigned long cmask,
 			ret = pmu_ctr_stop_hw(cidx);
 
 		if (cidx > (CSR_INSTRET - CSR_CYCLE) && flag & SBI_PMU_STOP_FLAG_RESET) {
+			if (pmu_dev && pmu_dev->hw_counter_disable_irq)
+				pmu_dev->hw_counter_disable_irq(cidx);
 			phs->active_events[cidx] = SBI_PMU_EVENT_IDX_INVALID;
 			pmu_reset_hw_mhpmevent(cidx);
 		}
@@ -1135,6 +1137,9 @@ void sbi_pmu_exit(struct sbi_scratch *scratch)
 	if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_10)
 		csr_write(CSR_MCOUNTEREN, -1);
 
+	if (sbi_platform_force_emulate_time_csr(sbi_platform_thishart_ptr()))
+		csr_clear(CSR_MCOUNTEREN, MCOUNTEREN_TM);
+
 	if (unlikely(!phs))
 		return;
 

lib/sbi/sbi_tlb.c

@@ -43,6 +43,10 @@ static void sbi_tlb_local_hfence_vvma(struct sbi_tlb_info *tinfo)
 
 	sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_VVMA_RCVD);
 
+	if (sbi_platform_local_hfence_vvma(
+			sbi_platform_thishart_ptr(), tinfo) == SBI_OK)
+		return;
+
 	hgatp = csr_swap(CSR_HGATP,
 			 (vmid << HGATP_VMID_SHIFT) & HGATP_VMID_MASK);
 
@@ -67,6 +71,10 @@ static void sbi_tlb_local_hfence_gvma(struct sbi_tlb_info *tinfo)
 
 	sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_GVMA_RCVD);
 
+	if (sbi_platform_local_hfence_gvma(
+			sbi_platform_thishart_ptr(), tinfo) == SBI_OK)
+		return;
+
 	if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) {
 		__sbi_hfence_gvma_all();
 		return;
@@ -85,6 +93,10 @@ static void sbi_tlb_local_sfence_vma(struct sbi_tlb_info *tinfo)
 
 	sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SFENCE_VMA_RCVD);
 
+	if (sbi_platform_local_sfence_vma(
+			sbi_platform_thishart_ptr(), tinfo) == SBI_OK)
+		return;
+
 	if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) {
 		__sbi_sfence_vma_all();
 		return;
@@ -108,6 +120,10 @@ static void sbi_tlb_local_hfence_vvma_asid(struct sbi_tlb_info *tinfo)
 
 	sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD);
 
+	if (sbi_platform_local_hfence_vvma_asid(
+			sbi_platform_thishart_ptr(), tinfo) == SBI_OK)
+		return;
+
 	hgatp = csr_swap(CSR_HGATP,
 			 (vmid << HGATP_VMID_SHIFT) & HGATP_VMID_MASK);
 
@@ -133,6 +149,10 @@ static void sbi_tlb_local_hfence_gvma_vmid(struct sbi_tlb_info *tinfo)
 
 	sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD);
 
+	if (sbi_platform_local_hfence_gvma_vmid(
+			sbi_platform_thishart_ptr(), tinfo) == SBI_OK)
+		return;
+
 	if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) {
 		__sbi_hfence_gvma_vmid(vmid);
 		return;
@@ -152,6 +172,10 @@ static void sbi_tlb_local_sfence_vma_asid(struct sbi_tlb_info *tinfo)
 
 	sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SFENCE_VMA_ASID_RCVD);
 
+	if (sbi_platform_local_sfence_vma_asid(
+			sbi_platform_thishart_ptr(), tinfo) == SBI_OK)
+		return;
+
 	/* Flush entire MM context for a given ASID */
 	if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) {
 		__asm__ __volatile__("sfence.vma x0, %0"
@@ -173,6 +197,10 @@ static void sbi_tlb_local_fence_i(struct sbi_tlb_info *tinfo)
 {
 	sbi_pmu_ctr_incr_fw(SBI_PMU_FW_FENCE_I_RECVD);
 
+	if (sbi_platform_local_fence_i(
+			sbi_platform_thishart_ptr(), tinfo) == SBI_OK)
+		return;
+
 	__asm__ __volatile("fence.i");
 }
 

lib/utils/gpio/Kconfig

@@ -18,6 +18,10 @@ config FDT_GPIO_SIFIVE
 	bool "SiFive GPIO FDT driver"
 	default n
 
+config FDT_GPIO_SOPHGO
+	bool "Sophgo GPIO FDT driver"
+	default n
+
 config FDT_GPIO_STARFIVE
 	bool "StarFive GPIO FDT driver"
 	default n