[LLVM][XTHeadVector] Implement intrinsics for vwfmul. (llvm#96)

* [LLVM][XTHeadVector] Define intrinsic functions.

* [LLVM][XTHeadVector] Define pseudos and pats.

* [LLVM][XTHeadVector] Add test cases.

* [NFC][XTHeadVector] Update Readme.

README.md

@@ -61,6 +61,7 @@ Any feature not listed below but present in the specification should be consider
     - (Done) `14.2. Vector Single-Width Floating-Point Add/Subtract Instructions`
     - (Done) `14.3. Vector Widening Floating-Point Add/Subtract Instructions`
     - (Done) `14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions`
+    - (Done) `14.5. Vector Widening Floating-Point Multiply`
 - (WIP) Clang intrinsics related to the `XTHeadVector` extension:
   - (WIP) `6. Configuration-Setting and Utility`
     - (Done) `6.1. Set vl and vtype`

llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td

@@ -898,6 +898,9 @@ let TargetPrefix = "riscv" in {
   defm th_vfdiv : XVBinaryAAXRoundingMode;
   defm th_vfrdiv : XVBinaryAAXRoundingMode;
 
+  // 14.5. Vector Widening Floating-Point Multiply
+  defm th_vfwmul : XVBinaryABXRoundingMode;
+
   // 16.1. Vector Mask-Register Logical Operations
   def int_riscv_th_vmand: RISCVBinaryAAAUnMasked;
   def int_riscv_th_vmnand: RISCVBinaryAAAUnMasked;

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td

@@ -2517,6 +2517,29 @@ multiclass XVPseudoVFRDIV_VF_RM {
   }
 }
 
+multiclass XVPseudoVWMUL_VV_VF_RM {
+  foreach m = MxListWXTHeadV in {
+    defvar mx = m.MX;
+    defvar WriteVFWMulV_MX = !cast<SchedWrite>("WriteVFWMulV_" # mx);
+    defvar ReadVFWMulV_MX = !cast<SchedRead>("ReadVFWMulV_" # mx);
+
+    defm "" : XVPseudoBinaryW_VV_RM<m>,
+              Sched<[WriteVFWMulV_MX, ReadVFWMulV_MX, ReadVFWMulV_MX, ReadVMask]>;
+  }
+
+  foreach f = FPListXTHeadV in {
+    foreach m = f.MxListFW in {
+      defvar mx = m.MX;
+      defvar WriteVFWMulF_MX = !cast<SchedWrite>("WriteVFWMulF_" # mx);
+      defvar ReadVFWMulV_MX = !cast<SchedRead>("ReadVFWMulV_" # mx);
+      defvar ReadVFWMulF_MX = !cast<SchedRead>("ReadVFWMulF_" # mx);
+
+      defm "" : XVPseudoBinaryW_VF_RM<m, f>,
+                Sched<[WriteVFWMulF_MX, ReadVFWMulV_MX, ReadVFWMulF_MX, ReadVMask]>;
+    }
+  }
+}
+
 multiclass XVPseudoVALU_MM {
   foreach m = MxListXTHeadV in {
     defvar mx = m.MX;
@@ -3980,6 +4003,18 @@ let Predicates = [HasVendorXTHeadV] in {
                             AllFloatXVectors, isSEWAware=1>;
 } // Predicates = [HasVendorXTHeadV]
 
+//===----------------------------------------------------------------------===//
+// 14.5. Vector Single-Width Floating-Point Add/Subtract Instructions
+//===----------------------------------------------------------------------===//
+let Predicates = [HasVendorXTHeadV], mayRaiseFPException = true, hasSideEffects = 0 in {
+  defm PseudoTH_VFWMUL : XVPseudoVWMUL_VV_VF_RM;
+}
+
+let Predicates = [HasVendorXTHeadV] in {
+  defm : XVPatBinaryW_VV_VX_RM<"int_riscv_th_vfwmul", "PseudoTH_VFWMUL",
+                               AllWidenableFloatXVectors>;
+}
+
 //===----------------------------------------------------------------------===//
 // 16.1. Vector Mask-Register Logical Operations
 //===----------------------------------------------------------------------===//