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RISCV Compressed Instructions (Zcb, Zcmp, Zcmt estensions) #169

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RISCV Compressed Instructions (Zcb, Zcmp, Zcmt estensions) #169

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2 changes: 1 addition & 1 deletion .gitmodules
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Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
[submodule "src/Emulator/Cores/tlib"]
path = src/Emulator/Cores/tlib
url = https://github.com/antmicro/tlib.git
url = https://github.com/SiliconLabsSoftware/renode-tlib.git
9 changes: 9 additions & 0 deletions src/Emulator/Cores/RiscV/BaseRiscV.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -1435,6 +1435,9 @@ public enum StandardInstructionSetExtensions
ZVE64D = 13,
ZACAS = 14,
SSCOFPMF = 15,
ZCB = 16,
ZCMP = 17,
ZCMT = 18,
}

public enum InterruptMode
Expand Down Expand Up @@ -1645,6 +1648,12 @@ private void HandleLongInstructionSetName(string name)
case "ZVE64F": standardExtensions.Add(StandardInstructionSetExtensions.ZVE64F); break;
case "ZVE64D": standardExtensions.Add(StandardInstructionSetExtensions.ZVE64D); break;
case "ZACAS": standardExtensions.Add(StandardInstructionSetExtensions.ZACAS); break;
case "ZCA":
instructionSets.Add(InstructionSet.C); // ZCA maps to base C extension
break;
case "ZCB": standardExtensions.Add(StandardInstructionSetExtensions.ZCB); break;
case "ZCMP": standardExtensions.Add(StandardInstructionSetExtensions.ZCMP); break;
case "ZCMT": standardExtensions.Add(StandardInstructionSetExtensions.ZCMT); break;
default:
throw new ConstructionException($"Undefined instructions set extension: '{name}'");
}
Expand Down
18 changes: 17 additions & 1 deletion src/Emulator/Cores/RiscV/RiscV32Registers.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -173,6 +173,20 @@ public override RegisterValue PC
}
}

[Register]
public RegisterValue JVT
{
get
{
return GetRegisterValue32((int)RiscV32Registers.JVT);
}

set
{
SetRegisterValue32((int)RiscV32Registers.JVT, value);
}
}

[Register]
public RegisterValue SSTATUS
{
Expand Down Expand Up @@ -871,6 +885,7 @@ protected override void InitializeRegisters()
{ RiscV32Registers.F31, new CPURegister(64, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F31" }) },
{ RiscV32Registers.FFLAGS, new CPURegister(65, 32, isGeneral: false, isReadonly: false, aliases: new [] { "FFLAGS" }) },
{ RiscV32Registers.FRM, new CPURegister(66, 32, isGeneral: false, isReadonly: false, aliases: new [] { "FRM" }) },
{ RiscV32Registers.JVT, new CPURegister(88, 32, isGeneral: false, isReadonly: false, aliases: new [] { "JVT" }) },
{ RiscV32Registers.VSTART, new CPURegister(101, 32, isGeneral: false, isReadonly: false, aliases: new [] { "VSTART" }) },
{ RiscV32Registers.VXSAT, new CPURegister(102, 32, isGeneral: false, isReadonly: false, aliases: new [] { "VXSAT" }) },
{ RiscV32Registers.VXRM, new CPURegister(103, 32, isGeneral: false, isReadonly: false, aliases: new [] { "VXRM" }) },
Expand Down Expand Up @@ -912,6 +927,7 @@ public enum RiscV32Registers
TP = 4,
FP = 8,
PC = 32,
JVT = 88,
SSTATUS = 321,
SIE = 325,
STVEC = 326,
Expand Down Expand Up @@ -1036,4 +1052,4 @@ public enum RiscV32Registers
F30 = 63,
F31 = 64,
}
}
}
18 changes: 17 additions & 1 deletion src/Emulator/Cores/RiscV/RiscV64Registers.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -173,6 +173,20 @@ public override RegisterValue PC
}
}

[Register]
public RegisterValue JVT
{
get
{
return GetRegisterValue64((int)RiscV64Registers.JVT);
}

set
{
SetRegisterValue64((int)RiscV64Registers.JVT, value);
}
}

[Register]
public RegisterValue SSTATUS
{
Expand Down Expand Up @@ -871,6 +885,7 @@ protected override void InitializeRegisters()
{ RiscV64Registers.F31, new CPURegister(64, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F31" }) },
{ RiscV64Registers.FFLAGS, new CPURegister(65, 32, isGeneral: false, isReadonly: false, aliases: new [] { "FFLAGS" }) },
{ RiscV64Registers.FRM, new CPURegister(66, 32, isGeneral: false, isReadonly: false, aliases: new [] { "FRM" }) },
{ RiscV64Registers.JVT, new CPURegister(88, 64, isGeneral: false, isReadonly: false, aliases: new [] { "JVT" }) },
{ RiscV64Registers.VSTART, new CPURegister(101, 64, isGeneral: false, isReadonly: false, aliases: new [] { "VSTART" }) },
{ RiscV64Registers.VXSAT, new CPURegister(102, 64, isGeneral: false, isReadonly: false, aliases: new [] { "VXSAT" }) },
{ RiscV64Registers.VXRM, new CPURegister(103, 64, isGeneral: false, isReadonly: false, aliases: new [] { "VXRM" }) },
Expand Down Expand Up @@ -912,6 +927,7 @@ public enum RiscV64Registers
TP = 4,
FP = 8,
PC = 32,
JVT = 88,
SSTATUS = 321,
SIE = 325,
STVEC = 326,
Expand Down Expand Up @@ -1036,4 +1052,4 @@ public enum RiscV64Registers
F30 = 63,
F31 = 64,
}
}
}
2 changes: 1 addition & 1 deletion src/Emulator/Cores/tlib
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Submodule tlib updated 8 files
+9 −0 arch/riscv/arch_exports.c
+6 −1 arch/riscv/cpu.h
+1 −0 arch/riscv/cpu_bits.h
+4 −0 arch/riscv/cpu_registers.c
+2 −0 arch/riscv/cpu_registers.h
+16 −0 arch/riscv/instmap.h
+14 −0 arch/riscv/op_helper.c
+453 −34 arch/riscv/translate.c