Main ASIC design files and project structure
timing/- Timing analysis and constraint scriptsanalysis/- RTL analysis and verification scriptsvalidation/- Test and validation scripts
uart/- UART-related firmware and executablestest/- Test programs and utilities- Root: Core firmware files (bootstrap, drivers)
SystemVerilog RTL files and testbenches
Timing constraint files (.sdc)
Documentation, guides, and reports
Generated timing and analysis reports
constraints/ip1_timing.sdc- Main timing constraintsscripts/timing/- Timing analysis toolstop/- Complete ASIC design hierarchy