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1. FPGA_Devel_RFSoc4x2_ScatterGatherMode_DMAloopback_HwSwCodesign FPGA_Devel_RFSoc4x2_ScatterGatherMode_DMAloopback_HwSwCodesign Public

   my work on RFSoc4*2 FPGA

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2. FPGA_devel_RFSoC4x2_Simple_Mode_DMA_plus_FIFO_loopback_design FPGA_devel_RFSoC4x2_Simple_Mode_DMA_plus_FIFO_loopback_design Public

   I Implemented from scratch the AXI DMA loopback with AXI4-Stream Data FIFO and proved the h/w design is working successfully with Vitis C code from Xylinx Standard Example.

   Tcl