armstub8.S sets RES0 bits in cptr_el3 #95

It moves 0x33ff into cptr_el3.

Cortex A53 TRM lists all bits except 10,20 and 31 as RES0.
Luckily, 0x33ff is a value where those 3 bits are 0 (and the 12 ON bits in the value are RES0 in the register), thus resulting in disabling of fp/simd traps to el3, as expected. Storing a zero into, or read-modify-write of, cptr_el3, would be proper.

The number 0x33ff fits more appropriately into cptr_el2, given the intention of disabling fp/simd traps to el2.