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32-bit bootstrap enabling caches but not the MMU #84
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[-]AArch32 bootstrap for RPi3 enabling caches but not the MMU[/-][+]32-bit bootstrap enabling caches but not the MMU[/+]on Nov 7, 2017 Have you experienced a problem with the current stub or are you just striving for correctness?
Just correctness, I was trying to understand what it was doing so that I could boot the kernel with multicore support from my own bootloader.
There's nothing wrong with that. You'll understand if this doesn't get fixed immediately, but it's on the list for a rainy day.
You could save us some time by answering a few questions:
- Your comment suggested th at ARM caches are inoperative without the MMU - is that true?
Never mind, I can answer this one myself - http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka13835.html says the I cache works but not the D cache. - Since the I cache may be enabled on entry to the kernel, do you see any reason not to since it will probably save a few cycles?
You could save even more time by submitting a Pull Request with an updated armstub7.S to review.
- Your comment suggested th at ARM caches are inoperative without the MMU - is that true?
Sure, I actually wanted someone else to confirm what I suspected.
I guess that the I cache can be left enabled, yes.
Sure, I can create a PR.
In the 32/bit bootstrap, caches are enabled:
tools/armstubs/armstub7.S
Lines 60 to 63 in b23276d
The MMU isn't enabled, though, so it is quite useless and those lines should probably be removed.
Also, according to the kernel docs, when booting the kernel,
The MMU must be off. Instruction cache may be on or off. Data cache must be off.:https://github.com/torvalds/linux/blob/8c27ceff3604b249a9efafbd1bd8b141b79e619d/Documentation/arm/Booting#L197-L200
This affects both ARMv7 and ARMv8 in AArch32, so RPi2 and RPi3.