Lab and project work of computer architecture
All the lab work is implemented in Verilog, and the course project is implemented using Python as a cover to use these verilog files.
Lab 1: Double Precision Floating Point Adder
Lab 2: Double Precision Floating Point Multiplier
Lab 3: Recursive doubling based carry-lookahead adder
Lab 4: 64 bit Wallace Tree Multiplier
Lab 5: Register file
Lab 6: Cache
Lab 7: 64-bit Logical unit
Project: Implementation of Tomasulo Algorithm