tweak timing

fastino_phy.py

@@ -390,6 +390,28 @@ def __init__(self, platform, n_channels=32, n_bits=16):
             self.comb += spi[i].ldacn.eq(0)
 
 
+class Aligner(Module):
+    def __init__(self, cd_fast="spi", cd_slow="sys"):
+        # the current fast period is fully contained within one slow period
+        self.aligned = Signal()
+
+        ###
+
+        slow = Signal(reset_less=True)
+        cd_slow = getattr(self.sync, cd_slow)
+        cd_slow += [
+            slow.eq(~slow),
+        ]
+        fast = Signal(reset_less=True)
+        cd_fast = getattr(self.sync, cd_fast)
+        cd_fast += [
+            fast.eq(slow),
+        ]
+        self.comb += [
+            self.aligned.eq(fast == slow),
+        ]
+
+
 class Fastino(Module):
     def __init__(self, platform):
         n_bits = 16
@@ -420,7 +442,8 @@ def __init__(self, platform):
             ("dac_clr", 1),
             ("clr_err", 1),
             ("led", 8),
-            ("reserved", 8),
+            ("typ", 4),
+            ("reserved", 4),
         ])
         unlock = Signal(reset=1)
 
@@ -538,7 +561,7 @@ def __init__(self, platform):
         self.submodules.int1 = ClockDomainsRenamer("spi")(Interpolator)(
             n_channels=16)
 
-        # no cdc, assume timing is comensurate such that
+        # no cdc, assume timing is synchronous and comensurate such that
         # max data delay sys-spi < min sys-spi clock delay over all alignments
         self.comb += [
             self.int0.stb.eq(self.frame.stb),
@@ -558,7 +581,6 @@ def __init__(self, platform):
 
         self.comb += [
             self.spi.stb.eq(self.int0.valid),
-            #self.spi.data.eq(self.frame.body[-len(self.spi.data):])
             self.spi.data.eq(Cat(
                 self.int0.en,
                 self.int1.en,

interpolator.py

@@ -21,8 +21,8 @@ def __init__(self, n_channels=16, n_bits=16, n_mantissa=6, n_exp=4,
         self.submodules += cic
         assert cic.latency < n_channels
 
-        rate_reset = Signal(n_channels)
-        enable_sr = Signal(2*n_channels)
+        rate_reset = Signal(n_channels, reset_less=True)
+        enable_sr = Signal(2*n_channels, reset_less=True)
         sr = [Signal(n_bits, reset_less=True)
               for _ in range(2*n_channels - cic.latency)]
 
@@ -45,7 +45,7 @@ def __init__(self, n_channels=16, n_bits=16, n_mantissa=6, n_exp=4,
             If(cic.xi == n_channels - 1,
                 cic.ce.eq(0),
             ),
-            If(self.stb & ~cic.ce,  # | (cic.xi == n_channels - 1),
+            If(self.stb,
                 Cat(sr[:n_channels]).eq(self.data[n_channels:]),
                 If(self.typ == 0,
                     enable_sr[cic.latency:cic.latency + n_channels].eq(