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QNX cleanup before tag #1054

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Merged
xwings merged 3 commits into from
Dec 29, 2021
Merged

QNX cleanup before tag #1054

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43d413d
Merge pull request #4 from qilingframework/dev
xwings Dec 29, 2021
1a8452c
realign broken ident
xwings Dec 29, 2021
16c3c4e
cleanup qnx
xwings Dec 29, 2021
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19 changes: 0 additions & 19 deletions qiling/os/linux/utils.py
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Original file line number Diff line number Diff line change
Expand Up @@ -3,23 +3,4 @@
# Cross Platform and Multi Architecture Advanced Binary Emulation Framework
#

"""
set_tls
"""
def ql_arm_init_get_tls(ql):
ql.mem.map(0xFFFF0000, 0x1000, info="[arm_tls]")
"""
'adr r0, data; ldr r0, [r0]; mov pc, lr; data:.ascii "\x00\x00"'
"""
sc = b'\x04\x00\x8f\xe2\x00\x00\x90\xe5\x0e\xf0\xa0\xe1\x00\x00\x00\x00'

# if ql.archendian == QL_ENDIAN.EB:
# sc = swap_endianess(sc)

ql.mem.write(ql.arch.arm_get_tls_addr, sc)
ql.log.debug("Set init_kernel_get_tls")

def swap_endianess(s: bytes, blksize=4) -> bytes:
blocks = (s[i:i + blksize] for i in range(0, len(s), blksize))

return b''.join(bytes(reversed(b)) for b in blocks)
17 changes: 2 additions & 15 deletions qiling/os/qnx/qnx.py
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Original file line number Diff line number Diff line change
Expand Up @@ -47,18 +47,6 @@ def __init__(self, ql: Qiling):
self.elf_mem_start = 0x0
self.load()

cc: QlCC = {
QL_ARCH.X86 : intel.cdecl,
QL_ARCH.X8664 : intel.amd64,
QL_ARCH.ARM : arm.aarch32,
QL_ARCH.ARM64 : arm.aarch64,
QL_ARCH.MIPS : mips.mipso32,
QL_ARCH.RISCV : riscv.riscv,
QL_ARCH.RISCV64: riscv.riscv,
}[ql.archtype](ql)

self.fcall = QlFunctionCall(ql, cc)

# use counters to get free Ids
self.channel_id = 1
# TODO: replace 0x400 with NR_OPEN from Qiling 1.25
Expand Down Expand Up @@ -101,7 +89,7 @@ def run_function_after_load(self):
f()


def hook_sigtrap(self, intno= None, int = None):
def hook_sigtrap(self, intno= None, int = None):
self.ql.log.info("Trap Found")
self.emu_error()
exit(1)
Expand All @@ -118,10 +106,9 @@ def run(self):
self.cpupage_tls_addr = int(self.ql.os.profile.get("OS32", "cpupage_tls_address"), 16)
self.tls_data_addr = int(self.ql.os.profile.get("OS32", "tls_data_address"), 16)
self.syspage_addr = int(self.ql.os.profile.get("OS32", "syspage_address"), 16)
syspage_path = os.path.join(self.ql.rootfs, "syspage.bin")
syspage_path = os.path.join(self.ql.rootfs, "syspage.bin")

self.ql.mem.map(self.syspage_addr, 0x4000, info="[syspage_mem]")


with open(syspage_path, "rb") as sp:
self.ql.mem.write(self.syspage_addr, sp.read())
Expand Down