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Merged
xwings merged 13 commits into from
Dec 16, 2021
Merged

Some STM32 updates #1040

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7dae9f4
Delete a dup typo of DAC
cla7aye15I4nd Dec 11, 2021
7a2b5ba
Add 'Flash Interface' into stm32f4 config
cla7aye15I4nd Dec 11, 2021
2892ef3
Merge branch 'dev' into stm32f4
cla7aye15I4nd Dec 12, 2021
44d4c35
elong the ppb segment
cla7aye15I4nd Dec 13, 2021
c6f72c7
Add device id in dbgmcu and fix critical typo
cla7aye15I4nd Dec 14, 2021
747413c
Add stn32 DBG struct
cla7aye15I4nd Dec 14, 2021
e010183
Add CRC Support
cla7aye15I4nd Dec 14, 2021
f59bff8
Refactor the gpio hook
cla7aye15I4nd Dec 14, 2021
6e34554
Update the hook_set/reset api
cla7aye15I4nd Dec 14, 2021
c45a0e6
Add stm32f407 CRC examples
cla7aye15I4nd Dec 14, 2021
75c84e1
Add a ML and oled example
cla7aye15I4nd Dec 14, 2021
aac25da
Delete useless import
cla7aye15I4nd Dec 15, 2021
2120d0f
Add header in example
cla7aye15I4nd Dec 15, 2021
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36 changes: 36 additions & 0 deletions examples/mcu/stm32f407_ai_sine_display.py
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Original file line number Diff line number Diff line change
@@ -0,0 +1,36 @@
#!/usr/bin/env python3
#
# Cross Platform and Multi Architecture Advanced Binary Emulation Framework
#

import sys
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@xwings xwings Dec 15, 2021

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missing header

sys.path.append("../..")

from qiling.core import Qiling
from qiling.const import QL_VERBOSE
from qiling.extensions.mcu.stm32f4 import stm32f407
from qiling.hw.external_device.oled.ssd1306 import PyGameSSD1306Spi


ql = Qiling(["../rootfs/mcu/stm32f407/ai-sine-test.elf"],
archtype="cortex_m", env=stm32f407, verbose=QL_VERBOSE.DEFAULT)

ql.hw.create('rcc')
ql.hw.create('pwr')
ql.hw.create('flash interface')
ql.hw.create('gpioa')
ql.hw.create('gpiob')
ql.hw.create('gpiod')
ql.hw.create('spi1')
ql.hw.create('crc')

oled = PyGameSSD1306Spi(dc=(ql.hw.gpiod, 5))
ql.hw.spi1.connect(oled)

def indicator(ql):
ql.log.info('PA7 set')

ql.hw.gpioa.hook_set(7, indicator, ql)
ql.hw.systick.ratio = 1000

ql.run(count=800000)
2 changes: 1 addition & 1 deletion examples/rootfs
Open in desktop
Submodule rootfs updated 3 files
+ − mcu/stm32f407/ai-sine-test.bin
+ − mcu/stm32f407/ai-sine-test.elf
+2,072 −0 mcu/stm32f407/ai-sine-test.hex
91 changes: 51 additions & 40 deletions qiling/extensions/mcu/stm32f4/stm32f401.py
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Original file line number Diff line number Diff line change
Expand Up @@ -7,17 +7,20 @@
"ADC1": {
"base": 0x40012000,
"struct": "STM32F4xxAdc",
"type": "periperal"
"type": "peripheral"
},
"CRC": {
"base": 0x40023000,
"struct": "STM32F4xxCrc",
"type": "periperal"
"type": "peripheral"
},
"DBGMCU": {
"base": 0xe0042000,
"struct": "STM32F4xxDbgmcu",
"type": "periperal"
"kwargs": {
"dev_id": 0x413,
},
"type": "core peripheral"
},
"DMA1": {
"base": 0x40026000,
Expand All @@ -32,7 +35,7 @@
"stream6_intn": 17,
"stream7_intn": 47
},
"type": "periperal"
"type": "peripheral"
},
"DMA2": {
"base": 0x40026400,
Expand All @@ -47,12 +50,12 @@
"stream6_intn": 69,
"stream7_intn": 70
},
"type": "periperal"
"type": "peripheral"
},
"EXTI": {
"base": 0x40013c00,
"struct": "STM32F4xxExti",
"type": "periperal"
"type": "peripheral"
},
"FLASH": {
"base": 0x8000000,
Expand All @@ -64,35 +67,43 @@
"size": 0x400,
"type": "memory"
},
"FLASH INTERFACE": {
"base": 0x40023c00,
"struct": "STM32F4xxFlash",
"kwargs": {
"intn": 4,
},
"type": "peripheral"
},
"GPIOA": {
"base": 0x40020000,
"struct": "STM32F4xxGpio",
"type": "periperal"
"type": "peripheral"
},
"GPIOB": {
"base": 0x40020400,
"struct": "STM32F4xxGpio",
"type": "periperal"
"type": "peripheral"
},
"GPIOC": {
"base": 0x40020800,
"struct": "STM32F4xxGpio",
"type": "periperal"
"type": "peripheral"
},
"GPIOD": {
"base": 0x40020c00,
"struct": "STM32F4xxGpio",
"type": "periperal"
"type": "peripheral"
},
"GPIOE": {
"base": 0x40021000,
"struct": "STM32F4xxGpio",
"type": "periperal"
"type": "peripheral"
},
"GPIOH": {
"base": 0x40021c00,
"struct": "STM32F4xxGpio",
"type": "periperal"
"type": "peripheral"
},
"I2C1": {
"base": 0x40005400,
Expand All @@ -101,7 +112,7 @@
"er_intn": 32,
"ev_intn": 31
},
"type": "periperal"
"type": "peripheral"
},
"I2C2": {
"base": 0x40005800,
Expand All @@ -110,7 +121,7 @@
"er_intn": 34,
"ev_intn": 33
},
"type": "periperal"
"type": "peripheral"
},
"I2C3": {
"base": 0x40005c00,
Expand All @@ -119,22 +130,22 @@
"er_intn": 73,
"ev_intn": 72
},
"type": "periperal"
"type": "peripheral"
},
"I2S2ext": {
"base": 0x40003400,
"struct": "STM32F4xxSpi",
"type": "periperal"
"type": "peripheral"
},
"I2S3ext": {
"base": 0x40004000,
"struct": "STM32F4xxSpi",
"type": "periperal"
"type": "peripheral"
},
"IWDG": {
"base": 0x40003000,
"struct": "STM32F4xxIwdg",
"type": "periperal"
"type": "peripheral"
},
"NVIC": {
"base": 0xe000e100,
Expand All @@ -154,21 +165,21 @@
},
"PPB": {
"base": 0xe0000000,
"size": 0x10000,
"size": 0x100000,
"type": "mmio"
},
"PWR": {
"base": 0x40007000,
"struct": "STM32F4xxPwr",
"type": "periperal"
"type": "peripheral"
},
"RCC": {
"base": 0x40023800,
"struct": "STM32F4xxRcc",
"kwargs": {
"intn": 5
},
"type": "periperal"
"type": "peripheral"
},
"RTC": {
"base": 0x40002800,
Expand All @@ -177,7 +188,7 @@
"alarm_intn": 41,
"wkup_intn": 3
},
"type": "periperal"
"type": "peripheral"
},
"SCB": {
"base": 0xe000ed00,
Expand All @@ -190,39 +201,39 @@
"kwargs": {
"intn": 49
},
"type": "periperal"
"type": "peripheral"
},
"SPI1": {
"base": 0x40013000,
"struct": "STM32F4xxSpi",
"kwargs": {
"intn": 35
},
"type": "periperal"
"type": "peripheral"
},
"SPI2": {
"base": 0x40003800,
"struct": "STM32F4xxSpi",
"kwargs": {
"intn": 36
},
"type": "periperal"
"type": "peripheral"
},
"SPI3": {
"base": 0x40003c00,
"struct": "STM32F4xxSpi",
"kwargs": {
"intn": 51
},
"type": "periperal"
"type": "peripheral"
},
"SPI4": {
"base": 0x40013400,
"struct": "STM32F4xxSpi",
"kwargs": {
"intn": 84
},
"type": "periperal"
"type": "peripheral"
},
"SRAM": {
"base": 0x20000000,
Expand All @@ -238,7 +249,7 @@
"SYSCFG": {
"base": 0x40013800,
"struct": "STM32F4xxSyscfg",
"type": "periperal"
"type": "peripheral"
},
"SYSTEM": {
"base": 0x1fff0000,
Expand All @@ -259,85 +270,85 @@
"trg_com_tim11_intn": 26,
"up_tim10_intn": 25
},
"type": "periperal"
"type": "peripheral"
},
"TIM10": {
"base": 0x40014400,
"struct": "STM32F4xxTim",
"type": "periperal"
"type": "peripheral"
},
"TIM11": {
"base": 0x40014800,
"struct": "STM32F4xxTim",
"type": "periperal"
"type": "peripheral"
},
"TIM2": {
"base": 0x40000000,
"struct": "STM32F4xxTim",
"kwargs": {
"intn": 28
},
"type": "periperal"
"type": "peripheral"
},
"TIM3": {
"base": 0x40000400,
"struct": "STM32F4xxTim",
"kwargs": {
"intn": 29
},
"type": "periperal"
"type": "peripheral"
},
"TIM4": {
"base": 0x40000800,
"struct": "STM32F4xxTim",
"kwargs": {
"intn": 30
},
"type": "periperal"
"type": "peripheral"
},
"TIM5": {
"base": 0x40000c00,
"struct": "STM32F4xxTim",
"kwargs": {
"intn": 50
},
"type": "periperal"
"type": "peripheral"
},
"TIM9": {
"base": 0x40014000,
"struct": "STM32F4xxTim",
"type": "periperal"
"type": "peripheral"
},
"USART1": {
"base": 0x40011000,
"struct": "STM32F4xxUsart",
"kwargs": {
"intn": 37
},
"type": "periperal"
"type": "peripheral"
},
"USART2": {
"base": 0x40004400,
"struct": "STM32F4xxUsart",
"kwargs": {
"intn": 38
},
"type": "periperal"
"type": "peripheral"
},
"USART6": {
"base": 0x40011400,
"struct": "STM32F4xxUsart",
"kwargs": {
"intn": 71
},
"type": "periperal"
"type": "peripheral"
},
"WWDG": {
"base": 0x40002c00,
"struct": "STM32F4xxWwdg",
"kwargs": {
"intn": 0
},
"type": "periperal"
"type": "peripheral"
}
}
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