Skip to content

Commit

Permalink
Release v0.2.12
Browse files Browse the repository at this point in the history
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
  • Loading branch information
niwis committed Aug 11, 2023
1 parent 481dedc commit 298b729
Showing 1 changed file with 4 additions and 0 deletions.
4 changes: 4 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,10 @@ All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).

## 0.2.12 - 2023-08-12
### Changed
- `tc_sram_xilinx`: Support ByteWidth != 8

## 0.2.11 - 2022-12-12
### Added
- `tc_clk_or2`: A new generic tech cell for balanced clock OR-gates.
Expand Down

0 comments on commit 298b729

Please sign in to comment.