Initial RDL implementation (replacing reggen)

.gitignore

@@ -9,7 +9,6 @@ scripts/compile_vsim.tcl
 work*
 !.github/workflows
 gf12
-Bender.lock
 tsmc65-test
 tsmc65
 bender

.gitlab-ci.yml

@@ -5,9 +5,9 @@
 # Author: Tim Fischer <fischeti@iis.ee.ethz.ch>
 
 variables:
-  VSIM: 'questa-2021.3-kgf vsim'
-  VCS: 'vcs-2020.12 vcs'
-  VLOGAN: 'vcs-2020.12 vlogan'
+  VSIM: 'questa-2025.1-dz vsim'
+  VCS: 'vcs-2025.06-dz vcs'
+  VLOGAN: 'vcs-2025.06-dz vlogan'
 
 stages:
   - build

Bender.lock

@@ -0,0 +1,38 @@
+packages:
+  apb:
+    revision: 77ddf073f194d44b9119949d2421be59789e69ae
+    version: 0.2.4
+    source:
+      Git: https://github.com/pulp-platform/apb.git
+    dependencies:
+    - common_cells
+  axi:
+    revision: f07498d53ecd5518b277c7d213ec3b71ca4df93c
+    version: 0.39.7
+    source:
+      Git: https://github.com/pulp-platform/axi.git
+    dependencies:
+    - common_cells
+    - common_verification
+    - tech_cells_generic
+  common_cells:
+    revision: 9afda9abb565971649c2aa0985639c096f351171
+    version: 1.38.0
+    source:
+      Git: https://github.com/pulp-platform/common_cells.git
+    dependencies:
+    - common_verification
+    - tech_cells_generic
+  common_verification:
+    revision: fb1885f48ea46164a10568aeff51884389f67ae3
+    version: 0.2.5
+    source:
+      Git: https://github.com/pulp-platform/common_verification.git
+    dependencies: []
+  tech_cells_generic:
+    revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
+    version: 0.2.13
+    source:
+      Git: https://github.com/pulp-platform/tech_cells_generic.git
+    dependencies:
+    - common_verification

Bender.yml

@@ -12,8 +12,8 @@ package:
 
 dependencies:
   common_cells:        { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.28.0 }
-  axi:                 { git: "https://github.com/pulp-platform/axi.git",                version: 0.38.0 }
-  register_interface:  { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8  }
+  axi:                 { git: "https://github.com/pulp-platform/axi.git",                version: 0.39.0 }
+  apb:                 { git: "https://github.com/pulp-platform/apb.git",                version: 0.2.4  }
 
 export_include_dirs:
   - src/axis/include
@@ -22,10 +22,10 @@ sources:
   files:
 
     # Configuration Registers
-    - src/regs/serial_link_reg_pkg.sv
-    - src/regs/serial_link_reg_top.sv
-    - src/regs/serial_link_single_channel_reg_pkg.sv
-    - src/regs/serial_link_single_channel_reg_top.sv
+    - src/regs/rtl/serial_link_reg_pkg.sv
+    - src/regs/rtl/serial_link_reg.sv
+    - src/regs/rtl/serial_link_single_channel_reg_pkg.sv
+    - src/regs/rtl/serial_link_single_channel_reg.sv
 
     # Parametrization
     - src/serial_link_pkg.sv
@@ -55,6 +55,8 @@ sources:
       - test/axi_channel_compare.sv
 
     - target: test
+      include_dirs:
+      - src/regs/rtl
       files:
       - test/tb_axi_serial_link.sv
       - test/tb_ch_calib_serial_link.sv

Makefile

@@ -6,8 +6,8 @@
 
 BENDER 		?= bender
 VSIM 		  ?= vsim
-REGGEN 		?= $(shell ${BENDER} path register_interface)/vendor/lowrisc_opentitan/util/regtool.py
 WORK 		  ?= work
+PEAKRDL 	?= peakrdl
 
 all: compile_questa
 
@@ -29,7 +29,6 @@ Bender.lock:
 
 clean_bender:
 	rm -rf .bender
-	rm -rf Bender.lock
 
 
 # --------------
@@ -38,10 +37,22 @@ clean_bender:
 
 .PHONY: update-regs
 
-update-regs: src/regs/*.hjson
-	echo $(REGGEN)
-	$(REGGEN) src/regs/serial_link.hjson -r -t src/regs
-	$(REGGEN) src/regs/serial_link_single_channel.hjson -r -t src/regs
+SLINK_NUM_CHANNELS ?= 38
+SLINK_LOG2_NUM_CHANNELS ?= 6
+SLINK_NUM_BITS ?= 16
+SLINK_LOG2_MAX_CLK_DIV ?= 10
+SLINK_LOG2_RAW_MODE_TX_FIFO_DEPTH ?= 3
+
+PEAKRDL_MC_PARAMETER_FLAGS := -P NumChannels=$(SLINK_NUM_CHANNELS) -P Log2NumChannels=$(SLINK_LOG2_NUM_CHANNELS)
+PEAKRDL_PARAMETER_FLAGS := -P NumBits=$(SLINK_NUM_BITS) -P Log2MaxClkDiv=$(SLINK_LOG2_MAX_CLK_DIV) -P Log2RawModeTXFifoDepth=$(SLINK_LOG2_RAW_MODE_TX_FIFO_DEPTH)
+
+update-regs: src/regs/rdl/*.rdl
+	$(PEAKRDL) regblock src/regs/rdl/serial_link.rdl -I src/regs/rdl -o src/regs/rtl/. --default-reset arst_n --cpuif apb4-flat $(PEAKRDL_MC_PARAMETER_FLAGS) $(PEAKRDL_PARAMETER_FLAGS)
+	$(PEAKRDL) regblock src/regs/rdl/serial_link_single_channel.rdl -I src/regs/rdl -o src/regs/rtl/. --default-reset arst_n --cpuif apb4-flat $(PEAKRDL_PARAMETER_FLAGS)
+	$(PEAKRDL) raw-header src/regs/rdl/serial_link.rdl -o src/regs/rtl/serial_link_addrmap.svh --format svh -I src/regs/rtl $(PEAKRDL_MC_PARAMETER_FLAGS) $(PEAKRDL_PARAMETER_FLAGS)
+	$(PEAKRDL) raw-header src/regs/rdl/serial_link_single_channel.rdl -o src/regs/rtl/serial_link_single_channel_addrmap.svh --format svh -I src/regs/rtl $(PEAKRDL_PARAMETER_FLAGS)
+	@sed -i '1i// Copyright 2025 ETH Zurich and University of Bologna.\n// Solderpad Hardware License, Version 0.51, see LICENSE for details.\n// SPDX-License-Identifier: SHL-0.51\n' src/regs/rtl/*.sv*
+
 
 # --------------
 # QuestaSim

README.md

@@ -39,7 +39,7 @@ For simple use cases with lower low bandwidth requirements (e.g. binary preloadi
 For use cases that require a higher bandwidth (e.g. Die2Die communication), a multi-channel configuration is recommended. In multi-channel configurations, each channel has its own source-synchronous forwarded clock and the channels are synchronized on the receiver side again. Further, a channel allocator handles faulty channels by redistributing the packets to functional channels. The detection of faulty channels can be done entirely in SW with a special _Raw Mode_ that decouples the link from the AXI interface and allows full controllability and observability of independent channels.
 
 ### Configuration Registers
-Single-channel and Multi-channels currently use different configuration register files because the multi-channel configuration requires additional registers for the channel allocator etc. The registers are generated with the [reggen](https://opentitan.org/book/util/reggen/index.html). The config files for single-channel (`serial_link_single_channel.hjson`) and multi-channel (`serial_link.hjson`) can be found in the `src/regs` folder and can be regenerated with the following command:
+Single-channel and Multi-channels currently use different configuration register files because the multi-channel configuration requires additional registers for the channel allocator etc. The registers are generated with [peakrdl](https://peakrdl-regblock.readthedocs.io/en/latest/). The SystemRDL config files for single-channel (`serial_link_single_channel.rdl`) and multi-channel (`serial_link.rdl`) can be found in the `src/regs/rdl` folder and can be regenerated with the following command:
 
 ```
 make update-regs

doc/README.md

@@ -19,8 +19,8 @@ The Serial Link has the following configuration Parameters:
 | `*_chan_t`    | `struct`       | AXI channel structs which matches `axi_req_t` and `axi_rsp_t`. Byproduct of `AXI_TYPEDEF` macro                                                                                                                         |
 | `cfg_req_t`   | `struct`       | `register_interface` request struct defined with `REG_BUS_TYPEDEF` macro                                                                                                                                                |
 | `cfg_rsp_t`   | `struct`       | `register_interface` response struct defined with `REG_BUS_TYPEDEF` macro                                                                                                                                               |
-| `hw2reg_t`    | `struct`       | struct that defines signals from the logic to the configuration registers generated by `reggen` e.g. `serial_link_reg_pkg::serial_link_hw2reg_t`                                                                        |
-| `reg2hw_t`    | `struct`       | struct that defines signals from the configuration registers defined by `reggen` to the logic e.g. `serial_link_reg_pkg::serial_link_reg2hw_t`                                                                          |
+| `hw2reg_t`    | `struct`       | struct that defines signals from the logic to the configuration registers generated by `peakrdl-regblock` e.g. `serial_link_reg_pkg::serial_link_reg__in_t`                                                                        |
+| `reg2hw_t`    | `struct`       | struct that defines signals from the configuration registers defined by `peakrdl-regblock` to the logic e.g. `serial_link_reg_pkg::serial_link_reg__out_t`                                                                          |
 | `NumChannels` | `int unsigned` | Number of Channels of the Serial Link. If `NumChannels > 1`, a *Channel Allocator* will be instantiated                                                                                                                 |
 | `NumLanes`    | `int unsigned` | Number of Lanes per Channel. Higher numbers reduce the wire overhead for the clocks for the source-synchronous interface but increase the timing complexity and defect probability. Recommended number of lanes are `8` |
 | `NumCredits`  | `int unsigned` | Number of outstanding payloads in flight that have not been processed yet by the other side. Be careful with increasing this parameter as it will increase the FIFOs inside the Serial Link.                            |

requirements.txt

@@ -2,4 +2,6 @@ hjson
 mistletoe
 mako
 pyyaml
-tabulate
+tabulate
+peakrdl
+peakrdl-rawheader @ git+https://github.com/micprog/PeakRDL-rawheader.git

src/regs/rdl/serial_link.rdl

@@ -0,0 +1,32 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Authors:
+//   - Michael Rogenmoser <michaero@iis.ee.ethz.ch>
+//   - Tim Fischer <fischeti@iis.ee.ethz.ch>
+
+`ifndef SERIAL_LINK_RDL
+`define SERIAL_LINK_RDL
+
+`include "serial_link_base.rdl"
+
+addrmap serial_link_reg #(
+    longint unsigned NumChannels = 38,
+    longint unsigned Log2NumChannels = 6,
+    longint unsigned NumBits = 16,
+    longint unsigned Log2MaxClkDiv = 10,
+    longint unsigned Log2RawModeTXFifoDepth = 3
+) {
+    default regwidth = 32;
+
+    serial_link_base #(
+        .NumChannels(NumChannels),
+        .Log2NumChannels(Log2NumChannels),
+        .NumBits(NumBits),
+        .Log2MaxClkDiv(Log2MaxClkDiv),
+        .Log2RawModeTXFifoDepth(Log2RawModeTXFifoDepth)
+    ) serial_link;
+};
+
+`endif // SERIAL_LINK_RDL