Adds snitch opcodes

- Makefile supports now enabling different sets of xpulp
- Makefile and parse_opcodes adapted to support snitch opcodes
- fixes some minor mistakes

Makefile

@@ -1,17 +1,49 @@
 SHELL := /bin/sh
 
 ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32h opcodes-rv64h opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-system
-ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-custom opcodes-rvv
+ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-custom
+# set with possible overlap
+# ALL_REAL_OPCODES += opcodes-rvv
+
 # Add here your opcodes
-XPULPIMG_OPCODES := opcodes-xpulpbitop_CUSTOM opcodes-xpulpbitopsmall_CUSTOM opcodes-xpulpbr_CUSTOM opcodes-xpulpclip_CUSTOM opcodes-xpulphwloop_CUSTOM opcodes-xpulpmacsi_CUSTOM opcodes-xpulpminmax_CUSTOM opcodes-xpulpslet_CUSTOM opcodes-xpulpvect_CUSTOM opcodes-xpulpvectshufflepack_CUSTOM
-MY_OPCODES := opcodes-frep_CUSTOM opcodes-xpulpimg_CUSTOM opcodes-rv32d-zfh_DRAFT opcodes-rv32q-zfh_DRAFT opcodes-rv32zfh_DRAFT opcodes-rv64zfh_DRAFT opcodes_sflt_CUSTOM
+XPULPIMG_OPCODES := opcodes-xpulpbr_CUSTOM
+XPULPIMG_OPCODES += opcodes-xpulpclip_CUSTOM
+XPULPIMG_OPCODES += opcodes-xpulpmacsi_CUSTOM
+XPULPIMG_OPCODES += opcodes-xpulpslet_CUSTOM
+XPULPIMG_OPCODES += opcodes-xpulpvect_CUSTOM
+XPULPIMG_OPCODES += opcodes-xpulpvectshufflepack_CUSTOM
+# sets with possible overlaps
+#XPULPIMG_OPCODES += opcodes-xpulpminmax_CUSTOM
+#XPULPIMG_OPCODES += opcodes-xpulphwloop_CUSTOM
+#XPULPIMG_OPCODES += opcodes-xpulpbitop_CUSTOM
+# XPULPIMG_OPCODES += opcodes-xpulpbitopsmall_CUSTOM #is a subset of opcodes-xpulpbitop_CUSTOM
+
+SNITCH_OPCODES := opcodes-dma
+SNITCH_OPCODES += opcodes-ipu
+SNITCH_OPCODES += opcodes-rep
+SNITCH_OPCODES += opcodes-ssr
+SNITCH_OPCODES += opcodes-rv32b_CUSTOM
+# sets with possible overlaps
+# SNITCH_OPCODES += opcodes-flt-occamy
+
+MY_OPCODES := opcodes-frep_CUSTOM
+MY_OPCODES += opcodes-rv32d-zfh_DRAFT opcodes-rv32q-zfh_DRAFT opcodes-rv32zfh_DRAFT opcodes-rv64zfh_DRAFT
+MY_OPCODES += opcodes-sflt_CUSTOM
+MY_OPCODES += $(XPULPIMG_OPCODES)
+#MY_OPCODES += $(SNITCH_OPCODES)
 
 ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) $(MY_OPCODES) opcodes-rvv-pseudo
 # Opcodes to be discarded
 DISCARDED_OPCODES := opcodes-frep_CUSTOM
 
 OPCODES = $(filter-out $(sort $(DISCARDED_OPCODES)), $(sort $(ALL_OPCODES)))
 
+# Snitch legacy opcode collection
+OPCODES_C  := $(ALL_REAL_OPCODES) $(XPULPIMG_OPCODES) opcodes-sflt_CUSTOM opcodes-ipu opcodes-dma
+OPCODES_SV := $(ALL_REAL_OPCODES) $(XPULPIMG_OPCODES) opcodes-sflt_CUSTOM opcodes-ipu
+OPCODES_PY := $(ALL_REAL_OPCODES) $(XPULPIMG_OPCODES)
+OPCODES_RS := $(ALL_REAL_OPCODES) $(XPULPIMG_OPCODES) opcodes-sflt_CUSTOM
+
 all: encoding_out.h inst.sverilog
 
 # Makefile inserted as prerequisite of every recipe because it can change due to DISCARDED_OPCODES
@@ -30,6 +62,19 @@ inst.chisel: $(OPCODES) parse_opcodes Makefile
 inst.go: $(ALL_REAL_ILEN32_OPCODES) parse_opcodes Makefile
 	cat $(ALL_REAL_ILEN32_OPCODES) | ./parse_opcodes -go > $@
 
+inst.c: $(OPCODES) parse_opcodes Makefile
+	cat $(OPCODES_C) | ./parse_opcodes -c > $@
+
+inst.sv: $(OPCODES) parse_opcodes Makefile
+	cat $(OPCODES_SV) | ./parse_opcodes -sv > $@
+
+inst.py: $(OPCODES) parse_opcodes Makefile
+	cat $(OPCODES_PY) | ./parse_opcodes -py > $@
+
+inst.rs: $(OPCODES) parse_opcodes Makefile
+	cat $(OPCODES_RS) | ./parse_opcodes -rust > $@
+	rustfmt $@
+
 inst.sverilog: $(OPCODES) parse_opcodes Makefile
 	cat $(OPCODES) | ./parse_opcodes -sverilog > $@
 

README.md

@@ -3,7 +3,7 @@ riscv-opcodes
 
 This repo enumerates standard RISC-V instruction opcodes and control and
 status registers, as well as some custom modifications.  It also contains a
-script to convert them into several formats (C, SystemVerilog, Scala, LaTeX),
+script to convert them into several formats (C, Python, Go, SystemVerilog, Scala, LaTeX),
 starting from their high-level, human-readable description.
 
 ## Practical info
@@ -37,3 +37,30 @@ starting from their high-level, human-readable description.
   (`opcodes-rvv` file) have been set as pseudo-instruction due to the overlapping
   of their opcodes space with the opcodes space of the SIMD instructions from
   Xpulpv2, defined in `opcodes-xpulpimg_CUSTOM`.
+
+
+## Smallfloat notice
+
+The Snitch cores use `opcodes-flt-occamy` to decode smallfloat instructions.
+`opcodes-sflt` is not used but describes how ariane (CVA6) decodes 
+instructions. This file is not used but kept in this repository for reference.
+Ariane and Snitch do not use the same FPU configuration.
+
+
+## Snitch notices
+`opcodes-sflt = opcodes-sflt_CUSTOM opcodes-rv32d-zfh_DRAFT opcodes-rv32q-zfh_DRAFT opcodes-rv32zfh_DRAFT opcodes-rv64zfh_DRAFT`
+for instructions `flb, fsb, fcvt.h.b, fcvt.b.h` an `@` is now used in front
+
+`opcodes-flt-occamy` will conflict with `opcodes-sflt_CUSTOM`, `opcodes-rv32d-zfh_DRAFT`, `opcodes-rv32q-zfh_DRAFT`, `opcodes-rv32zfh_DRAFT`, `opcodes-rv64zfh_DRAFT`
+
+`hfence.bvma` was renamed to `hfence.vvma` (same opcode)
+
+the RV32B opcodes were put into its own custom file `opcodes-rv32b_CUSTOM`
+
+## Overlap notices
+`opcodes-rvv` and `opcodes-xpulpbitop` overlap
+`opcodes-xpulpbitop` is superset of `opcodes-xpulpbitopsmall`
+`opcodes-flt-occamy` overlaps `opcodes-sflt_CUSTOM`, `opcodes-rv32d-zfh_DRAFT`, `opcodes-rv32q-zfh_DRAFT`, `opcodes-rv32zfh_DRAFT`, `opcodes-rv64zfh_DRAFT`
+`opcodes-rv32b_CUSTOM` overlaps `opcodes-xpulpbitop`,`opcodes-xpulpbitopsmall`
+`opcodes-xpulphwloop_CUSTOM` overlaps `opcodes-ipu`
+`opcodes-minmax` overlaps `opcodes-rv32b_CUSTOM`