Arc assembler: Convert nps400 from a machine type to an extension.

gas	* config/tc-arc.c (check_cpu_feature, md_parse_option):
	Add nps400 option and feature. Add check for nps400
	feature. Refactor existing checks to check subclass before
	feature enablement.
	(md_show_usage): Document flags for NPS-400 and add some other
	undocumented flags.
	(cpu_type): Remove nps400 CPU type entry
	(check_zol): Remove bfd_mach_arc_nps400 case.
	(md_show_usage): Add help on -mcpu=nps400.
	(cpu_types): Add entry for nps400 as arc700 plus nps400 extension
	set.
	* doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and
	-fpuda flags.  Document -mcpu=nps400.
	* testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change
	expected flags to match ARC700 instead of NPS400.
	* testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400.
	* testsuite/gas/arc/nps-400-2.d: Likewise.
	* testsuite/gas/arc/nps-400-3.d: Likewise.
	* testsuite/gas/arc/nps-400-4.d: Likewise.
	* testsuite/gas/arc/nps-400-5.d: Likewise.
	* testsuite/gas/arc/nps-400-6.d: Likewise.
	* testsuite/gas/arc/nps-400-7.d: Likewise.
	* testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to
	avoid clash with cbba instruction.
	* testsuite/gas/arc/textinsn2op01.d: Likewise.
	* testsuite/gas/arc/textinsn3op.d: Likewise.
	* testsuite/gas/arc/textinsn3op.s: Likewise.
	* testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using
	-mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags.

binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400
	case.

ld	* testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400.
	* testsuite/ld-arc/nps-1b.d: Likewise.

include	* opcode/arc.h: Add nps400 extension and instruction
	subclass.
	Remove ARC_OPCODE_NPS400
	* elf/arc.h: Remove E_ARC_MACH_NPS400

opcodes	* arc-dis.c (arc_insn_length): Add comment on instruction length.
	Use same method for determining	instruction length on ARC700 and
	NPS-400.
	(arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
	* arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
	with the NPS400 subclass.
	* arc-opc.c: Likewise.

bfd	* archures.c: Remove bfd_mach_arc_nps400.
	* bfd-in2.h: Likewise.
	* cpu-arc.c (arch_info_struct): Likewise.
	* elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing):
	Likewise.

bfd/ChangeLog

@@ -1,3 +1,11 @@
+2016-06-21  Graham Markall  <graham.markall@embecosm.com>
+
+	* archures.c: Remove bfd_mach_arc_nps400.
+	* bfd-in2.h: Likewise.
+	* cpu-arc.c (arch_info_struct): Likewise.
+	* elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing):
+	Likewise.
+
 2016-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR ld/18250

bfd/archures.c

@@ -375,7 +375,6 @@ DESCRIPTION
 .#define bfd_mach_arc_arc601    4
 .#define bfd_mach_arc_arc700    3
 .#define bfd_mach_arc_arcv2     5
-.#define bfd_mach_arc_nps400    6
 . bfd_arch_m32c,     {* Renesas M16C/M32C.  *}
 .#define bfd_mach_m16c        0x75
 .#define bfd_mach_m32c        0x78

bfd/bfd-in2.h

@@ -2186,7 +2186,6 @@ enum bfd_architecture
 #define bfd_mach_arc_arc601    4
 #define bfd_mach_arc_arc700    3
 #define bfd_mach_arc_arcv2     5
-#define bfd_mach_arc_nps400    6
  bfd_arch_m32c,     /* Renesas M16C/M32C.  */
 #define bfd_mach_m16c        0x75
 #define bfd_mach_m32c        0x78

bfd/cpu-arc.c

@@ -47,9 +47,8 @@ static const bfd_arch_info_type arch_info_struct[] =
   ARC (bfd_mach_arc_arc601, "ARC601", FALSE, &arch_info_struct[3]),
   ARC (bfd_mach_arc_arc700, "ARC700", FALSE, &arch_info_struct[4]),
   ARC (bfd_mach_arc_arc700, "A7",     FALSE, &arch_info_struct[5]),
-  ARC (bfd_mach_arc_nps400, "NPS400", FALSE, &arch_info_struct[6]),
-  ARC (bfd_mach_arc_arcv2,  "ARCv2",  FALSE, &arch_info_struct[7]),
-  ARC (bfd_mach_arc_arcv2,  "EM",     FALSE, &arch_info_struct[8]),
+  ARC (bfd_mach_arc_arcv2,  "ARCv2",  FALSE, &arch_info_struct[6]),
+  ARC (bfd_mach_arc_arcv2,  "EM",     FALSE, &arch_info_struct[7]),
   ARC (bfd_mach_arc_arcv2,  "HS",     FALSE, NULL),
 };
 

bfd/elf32-arc.c

@@ -621,9 +621,6 @@ arc_elf_object_p (bfd * abfd)
 	  case E_ARC_MACH_ARC700:
 	    mach = bfd_mach_arc_arc700;
 	    break;
-	  case E_ARC_MACH_NPS400:
-	    mach = bfd_mach_arc_nps400;
-	    break;
 	  case EF_ARC_CPU_ARCV2HS:
 	  case EF_ARC_CPU_ARCV2EM:
 	    mach = bfd_mach_arc_arcv2;
@@ -673,9 +670,6 @@ arc_elf_final_write_processing (bfd * abfd,
     case bfd_mach_arc_arc700:
       emf = EM_ARC_COMPACT;
       break;
-    case bfd_mach_arc_nps400:
-      emf = EM_ARC_COMPACT;
-      break;
     case bfd_mach_arc_arcv2:
       emf = EM_ARC_COMPACT2;
       break;

binutils/ChangeLog

@@ -1,3 +1,8 @@
+2016-06-21  Graham Markall  <graham.markall@embecosm.com>
+
+	* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400
+	case.
+
 2016-06-15  Nick Clifton  <nickc@redhat.com>
 
 	* readelf.c (is_24bit_abs_reloc): Add support for R_FT32_20

binutils/readelf.c

@@ -2381,9 +2381,6 @@ decode_ARC_machine_flags (unsigned e_flags, unsigned e_machine, char buf[])
     case E_ARC_MACH_ARC700:
       strcat (buf, ", ARC700");
       break;
-    case E_ARC_MACH_NPS400:
-      strcat (buf, ", NPS400");
-      break;
 
       /* The only times we should end up here are (a) A corrupt ELF, (b) A
          new ELF with new architecture being read by an old version of

gas/ChangeLog

@@ -1,3 +1,35 @@
+2016-06-21  Graham Markall  <graham.markall@embecosm.com>
+
+	* config/tc-arc.c (check_cpu_feature, md_parse_option):
+	Add nps400 option and feature. Add check for nps400
+	feature. Refactor existing checks to check subclass before
+	feature enablement.
+	(md_show_usage): Document flags for NPS-400 and add some other
+	undocumented flags.
+	(cpu_type): Remove nps400 CPU type entry
+	(check_zol): Remove bfd_mach_arc_nps400 case.
+	(md_show_usage): Add help on -mcpu=nps400.
+	(cpu_types): Add entry for nps400 as arc700 plus nps400 extension
+	set.
+	* doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and
+	-fpuda flags.  Document -mcpu=nps400.
+	* testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change
+	expected flags to match ARC700 instead of NPS400.
+	* testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400.
+	* testsuite/gas/arc/nps-400-2.d: Likewise.
+	* testsuite/gas/arc/nps-400-3.d: Likewise.
+	* testsuite/gas/arc/nps-400-4.d: Likewise.
+	* testsuite/gas/arc/nps-400-5.d: Likewise.
+	* testsuite/gas/arc/nps-400-6.d: Likewise.
+	* testsuite/gas/arc/nps-400-7.d: Likewise.
+	* testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to
+	avoid clash with cbba instruction.
+	* testsuite/gas/arc/textinsn2op01.d: Likewise.
+	* testsuite/gas/arc/textinsn3op.d: Likewise.
+	* testsuite/gas/arc/textinsn3op.s: Likewise.
+	* testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using
+	-mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags.
+
 2016-06-20  Maciej W. Rozycki  <macro@imgtec.com>
 
 	* testsuite/gas/mips/r6-64-n32.d: Change the `name' tag.

gas/config/tc-arc.c

@@ -100,6 +100,7 @@ enum arc_rlx_types
 #define is_fpuda_p(op)          (((sc) == DPA))
 #define is_br_jmp_insn_p(op)    (((op)->insn_class == BRANCH || (op)->insn_class == JUMP))
 #define is_kernel_insn_p(op)    (((op)->insn_class == KERNEL))
+#define is_nps400_p(op)         (((sc) == NPS400))
 
 /* Generic assembler global variables which must be defined by all
    targets.  */
@@ -179,6 +180,7 @@ enum options
   OPTION_MCPU,
   OPTION_CD,
   OPTION_RELAX,
+  OPTION_NPS400,
 
   /* The following options are deprecated and provided here only for
      compatibility reasons.  */
@@ -221,6 +223,7 @@ struct option md_longopts[] =
   { "mHS",		no_argument,	   NULL, OPTION_ARCHS },
   { "mcode-density",	no_argument,	   NULL, OPTION_CD },
   { "mrelax",           no_argument,       NULL, OPTION_RELAX },
+  { "mnps400",          no_argument,       NULL, OPTION_NPS400 },
 
   /* The following options are deprecated and provided here only for
      compatibility reasons.  */
@@ -425,8 +428,8 @@ static const struct cpu_type
     E_ARC_MACH_ARC600,  0x00},
   { "arc700", ARC_OPCODE_ARC700,  bfd_mach_arc_arc700,
     E_ARC_MACH_ARC700,  0x00},
-  { "nps400", ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400, bfd_mach_arc_nps400,
-    E_ARC_MACH_NPS400,  0x00},
+  { "nps400", ARC_OPCODE_ARC700 , bfd_mach_arc_arc700,
+    E_ARC_MACH_ARC700,  ARC_NPS400},
   { "arcem",  ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
     EF_ARC_CPU_ARCV2EM, 0x00},
   { "archs",  ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
@@ -1529,20 +1532,19 @@ allocate_tok (expressionS *tok, int ntok, int cidx)
 static bfd_boolean
 check_cpu_feature (insn_subclass_t sc)
 {
-  if (!(arc_features & ARC_CD)
-      && is_code_density_p (sc))
+  if (is_code_density_p (sc) && !(arc_features & ARC_CD))
     return FALSE;
 
-  if (!(arc_features & ARC_SPFP)
-      && is_spfp_p (sc))
+  if (is_spfp_p (sc) && !(arc_features & ARC_SPFP))
     return FALSE;
 
-  if (!(arc_features & ARC_DPFP)
-      && is_dpfp_p (sc))
+  if (is_dpfp_p (sc) && !(arc_features & ARC_DPFP))
     return FALSE;
 
-  if (!(arc_features & ARC_FPUDA)
-      && is_fpuda_p (sc))
+  if (is_fpuda_p (sc) && !(arc_features & ARC_FPUDA))
+    return FALSE;
+
+  if (is_nps400_p (sc) && !(arc_features & ARC_NPS400))
     return FALSE;
 
   return TRUE;
@@ -3341,6 +3343,9 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
       relaxation_state = 1;
       break;
 
+    case OPTION_NPS400:
+      arc_features |= ARC_NPS400;
+
     case OPTION_USER_MODE:
     case OPTION_LD_EXT_MASK:
     case OPTION_SWAP:
@@ -3396,6 +3401,18 @@ md_show_usage (FILE *stream)
   fprintf (stream, _("ARC-specific assembler options:\n"));
 
   fprintf (stream, "  -mcpu=<cpu name>\t  assemble for CPU <cpu name>\n");
+  fprintf (stream, "  -mcpu=nps400\t\t  same as -mcpu=arc700 -mnps400\n");
+  fprintf (stream, "  -mA6/-mARC600/-mARC601  same as -mcpu=arc600\n");
+  fprintf (stream, "  -mA7/-mARC700\t\t  same as -mcpu=arc700\n");
+  fprintf (stream, "  -mEM\t\t\t  same as -mcpu=arcem\n");
+  fprintf (stream, "  -mHS\t\t\t  same as -mcpu=archs\n");
+
+  fprintf (stream, "  -mnps400\t\t  enable NPS-400 extended instructions\n");
+  fprintf (stream, "  -mspfp\t\t  enable single-precision floating point instructions\n");
+  fprintf (stream, "  -mdpfp\t\t  enable double-precision floating point instructions\n");
+  fprintf (stream, "  -mfpuda\t\t  enable double-precision assist floating "
+                   "point\n\t\t\t  instructions for ARC EM\n");
+
   fprintf (stream,
 	   "  -mcode-density\t  enable code density option for ARC EM\n");
 
@@ -3404,8 +3421,36 @@ md_show_usage (FILE *stream)
   fprintf (stream, _("\
   -EL                     assemble code for a little-endian cpu\n"));
   fprintf (stream, _("\
-  -mrelax                  Enable relaxation\n"));
-
+  -mrelax                 enable relaxation\n"));
+
+  fprintf (stream, _("The following ARC-specific assembler options are "
+                     "deprecated and are accepted\nfor compatibility only:\n"));
+
+  fprintf (stream, _("  -mEA\n"
+                     "  -mbarrel-shifter\n"
+                     "  -mbarrel_shifter\n"
+                     "  -mcrc\n"
+                     "  -mdsp-packa\n"
+                     "  -mdsp_packa\n"
+                     "  -mdvbf\n"
+                     "  -mld-extension-reg-mask\n"
+                     "  -mlock\n"
+                     "  -mmac-24\n"
+                     "  -mmac-d16\n"
+                     "  -mmac_24\n"
+                     "  -mmac_d16\n"
+                     "  -mmin-max\n"
+                     "  -mmin_max\n"
+                     "  -mmul64\n"
+                     "  -mno-mpy\n"
+                     "  -mnorm\n"
+                     "  -mrtsc\n"
+                     "  -msimd\n"
+                     "  -mswap\n"
+                     "  -mswape\n"
+                     "  -mtelephony\n"
+		     "  -muser-mode-only\n"
+                     "  -mxy\n"));
 }
 
 /* Find the proper relocation for the given opcode.  */
@@ -4070,7 +4115,6 @@ check_zol (symbolS *s)
 end of the ZOL label @%s"), S_GET_NAME (s));
 
       /* Fall through.  */
-    case bfd_mach_arc_nps400:
     case bfd_mach_arc_arc700:
       if (arc_last_insns[0].has_delay_slot)
 	as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),

gas/doc/as.texinfo

@@ -2680,7 +2680,7 @@ do include file processing with the @code{.include} directive
 (@pxref{Include,,@code{.include}}).  You can use the @sc{gnu} C compiler driver
 to get other ``CPP'' style preprocessing by giving the input file a
 @samp{.S} suffix.  @xref{Overall Options, ,Options Controlling the Kind of
-Output, gcc.info, Using GNU CC}.
+Output, gcc.info, Using GNU CC} .
 
 Excess whitespace, comments, and character constants
 cannot be used in the portions of the input text that are not

gas/doc/c-arc.texi

@@ -56,9 +56,6 @@ Assemble for ARC 601.  Alias: @code{-mARC601}.
 @cindex @code{mARC700} command line option, ARC
 Assemble for ARC 700.  Aliases: @code{-mA7}, @code{-mARC700}.
 
-@item nps400
-Assemble for NPS400.
-
 @item arcem
 @cindex @code{mEM} command line option, ARC
 Assemble for ARC EM.  Aliases: @code{-mEM}
@@ -67,6 +64,10 @@ Assemble for ARC EM.  Aliases: @code{-mEM}
 @cindex @code{mHS} command line option, ARC
 Assemble for ARC HS.  Aliases: @code{-mHS}, @code{-mav2hs}.
 
+@item nps400
+@cindex @code{mnps400} command line option, ARC
+Assemble for ARC 700 with NPS-400 extended instructions.
+
 @end table
 
 Note: the @code{.cpu} directive (@pxref{ARC Directives}) can
@@ -94,6 +95,23 @@ Enable support for assembly-time relaxation.  The assembler will
 replace a longer version of an instruction with a shorter one,
 whenever it is possible.
 
+@cindex @code{-mnps400} command line option, ARC
+@item -mnps400
+Enable support for NPS-400 extended instructions.
+
+@cindex @code{-mspfp} command line option, ARC
+@item -mspfp
+Enable support for single-precision floating point instructions.
+
+@cindex @code{-mdpfp} command line option, ARC
+@item -mdpfp
+Enable support for double-precision floating point instructions.
+
+@cindex @code{-mfpuda} command line option, ARC
+@item -mfpuda
+Enable support for double-precision assist floating point instructions.
+Only valid for ARC EM processors.
+
 @end table
 
 @node ARC Syntax

gas/testsuite/gas/arc/nps400-0.d

@@ -11,5 +11,5 @@
   Machine:                           ARCompact
   Version:                           0x1
 #...
-  Flags:                             0x307, NPS400, v3 no-legacy-syscalls ABI
-#...
+  Flags:                             0x303, ARC700, v3 no-legacy-syscalls ABI
+#...

gas/testsuite/gas/arc/nps400-1.d

@@ -1,4 +1,4 @@
-#as: -mcpu=nps400
+#as: -mcpu=arc700 -mnps400
 #objdump: -dr
 
 .*: +file format .*arc.*

gas/testsuite/gas/arc/nps400-2.d

@@ -1,4 +1,4 @@
-#as: -mcpu=nps400
+#as: -mcpu=arc700 -mnps400
 #objdump: -dr
 
 .*: +file format .*arc.*

gas/testsuite/gas/arc/nps400-3.d

@@ -1,4 +1,4 @@
-#as: -mcpu=nps400
+#as: -mcpu=arc700 -mnps400
 #objdump: -dr
 
 .*: +file format .*arc.*

gas/testsuite/gas/arc/nps400-4.d

@@ -1,4 +1,4 @@
-#as: -mcpu=nps400
+#as: -mcpu=arc700 -mnps400
 #objdump: -dr
 
 .*: +file format .*arc.*

gas/testsuite/gas/arc/nps400-5.d

@@ -1,4 +1,4 @@
-#as: -mcpu=nps400
+#as: -mcpu=arc700 -mnps400
 #objdump: -dr
 
 .*: +file format .*arc.*

gas/testsuite/gas/arc/nps400-6.d

@@ -1,4 +1,4 @@
-#as: -mcpu=nps400
+#as: -mcpu=arc700 -mnps400
 #objdump: -dr
 
 .*: +file format .*arc.*

gas/testsuite/gas/arc/nps400-7.d

@@ -1,4 +1,4 @@
-#as: -mcpu=nps400
+#as: -mcpu=arc700 -mnps400
 #objdump: -dr
 
 .*: +file format .*arc.*

gas/testsuite/gas/arc/textinsn2op01.d

@@ -6,22 +6,22 @@
 Disassembly of section .text:
 
 [0-9a-f]+ <.text>:
-   0:	382d 007e           	myinsn	r0,r1
-   4:	3b2d 373e           	myinsn	fp,sp
-   8:	386d 003e           	myinsn	r0,0
-   c:	392d 0fbe ffff ffff 	myinsn	r1,0xffffffff
-  14:	3eed 7080 0000 0000 	myinsn	0,r2
-  1c:	3c2d 0fbe 0000 00ff 	myinsn	r4,0xff
-  24:	3e2d 0fbe ffff ff00 	myinsn	r6,0xffffff00
-  2c:	382d 1fbe 0000 0100 	myinsn	r8,0x100
-  34:	392d 1fbe ffff feff 	myinsn	r9,0xfffffeff
-  3c:	3b2d 1fbe 4242 4242 	myinsn	r11,0x42424242
-  44:	382d 0fbe 0000 0000 	myinsn	r0,0
+   0:	3830 007e           	myinsn	r0,r1
+   4:	3b30 373e           	myinsn	fp,sp
+   8:	3870 003e           	myinsn	r0,0
+   c:	3930 0fbe ffff ffff 	myinsn	r1,0xffffffff
+  14:	3ef0 7080 0000 0000 	myinsn	0,r2
+  1c:	3c30 0fbe 0000 00ff 	myinsn	r4,0xff
+  24:	3e30 0fbe ffff ff00 	myinsn	r6,0xffffff00
+  2c:	3830 1fbe 0000 0100 	myinsn	r8,0x100
+  34:	3930 1fbe ffff feff 	myinsn	r9,0xfffffeff
+  3c:	3b30 1fbe 4242 4242 	myinsn	r11,0x42424242
+  44:	3830 0fbe 0000 0000 	myinsn	r0,0
 			48: R_ARC_32_ME	foo
-  4c:	382d 807e           	myinsn.f	r0,r1
-  50:	3a6d 807e           	myinsn.f	r2,0x1
-  54:	3eed f100 0000 0000 	myinsn.f	0,r4
-  5c:	3d2d 8fbe 0000 0200 	myinsn.f	r5,0x200
-  64:	3eed f102 0000 0000 	myinsn.ne.f	0,r4
-  6c:	3eed ff85 dead beef 	myinsn.c.f	0xdeadbeef,0xdeadbeef
-  74:	3eed f0a6 dead beef 	myinsn.nc.f	0xdeadbeef,0x2
+  4c:	3830 807e           	myinsn.f	r0,r1
+  50:	3a70 807e           	myinsn.f	r2,0x1
+  54:	3ef0 f100 0000 0000 	myinsn.f	0,r4
+  5c:	3d30 8fbe 0000 0200 	myinsn.f	r5,0x200
+  64:	3ef0 f102 0000 0000 	myinsn.ne.f	0,r4
+  6c:	3ef0 ff85 dead beef 	myinsn.c.f	0xdeadbeef,0xdeadbeef
+  74:	3ef0 f0a6 dead beef 	myinsn.nc.f	0xdeadbeef,0x2