include/opcode/

	* ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
opcodes/
	* ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
	* ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
	(PPCVEC2, PPCTMR, E6500): New short names.
	(powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
	mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
	lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
	lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
	lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
	optional operands on sync instruction for E6500 target.
bfd/
	* archures.c: Add bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500.
	* bfd-in2.h: Regenerate.
	* cpu-powerpc.c (bfd_powerpc_archs): Add entryies for
	bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500.
gas/
	* config/tc-ppc.c (md_show_usage): Document -me5500 and -me6500.
	(ppc_handle_align): Add termination nop opcode for e500mc family.
	* doc/as.texinfo: Document options -me5500 and -me6500.
	* doc/c-ppc.texi: Likewise.
gas/testsuite/
	* gas/ppc/e500mc64_nop.s: New test case for e500mc family
	termination nops.
	* gas/ppc/e500mc64_nop.d: Likewise.
	* gas/ppc/e5500_nop.s: Likewise.
	* gas/ppc/e5500_nop.d: Likewise.
	* gas/ppc/e6500_nop.s: Likewise.
	* gas/ppc/e6500_nop.d: Likewise.
	* gas/ppc/e6500.s: New.
	* gas/ppc/e6500.d: Likewise.
	* gas/ppc/ppc.exp: Run e6500, e500mc64_nop, e5500_nop, and e6500_nop.

bfd/ChangeLog

@@ -1,3 +1,10 @@
+2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
+
+	* archures.c: Add bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500.
+	* bfd-in2.h: Regenerate.
+	* cpu-powerpc.c (bfd_powerpc_archs): Add entries for
+	bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500.
+
 2012-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR ld/13817

bfd/archures.c

@@ -1,7 +1,7 @@
 /* BFD library support routines for architectures.
    Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
-   Free Software Foundation, Inc.
+   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
+   2012 Free Software Foundation, Inc.
    Hacked by John Gilmore and Steve Chamberlain of Cygnus Support.
 
    This file is part of BFD, the Binary File Descriptor library.
@@ -241,6 +241,8 @@ DESCRIPTION
 .#define bfd_mach_ppc_e500      500
 .#define bfd_mach_ppc_e500mc    5001
 .#define bfd_mach_ppc_e500mc64  5005
+.#define bfd_mach_ppc_e5500     5006
+.#define bfd_mach_ppc_e6500     5007
 .#define bfd_mach_ppc_titan     83
 .  bfd_arch_rs6000,    {* IBM RS/6000 *}
 .#define bfd_mach_rs6k		6000

bfd/bfd-in2.h

@@ -1947,6 +1947,8 @@ enum bfd_architecture
 #define bfd_mach_ppc_e500      500
 #define bfd_mach_ppc_e500mc    5001
 #define bfd_mach_ppc_e500mc64  5005
+#define bfd_mach_ppc_e5500     5006
+#define bfd_mach_ppc_e6500     5007
 #define bfd_mach_ppc_titan     83
   bfd_arch_rs6000,    /* IBM RS/6000 */
 #define bfd_mach_rs6k          6000

bfd/cpu-powerpc.c

@@ -1,6 +1,6 @@
 /* BFD PowerPC CPU definition
-   Copyright 1994, 1995, 1996, 2000, 2001, 2002, 2003, 2005, 2007, 2008, 2010
-   Free Software Foundation, Inc.
+   Copyright 1994, 1995, 1996, 2000, 2001, 2002, 2003, 2005, 2007, 2008,
+   2010, 2012 Free Software Foundation, Inc.
    Contributed by Ian Lance Taylor, Cygnus Support.
 
    This file is part of BFD, the Binary File Descriptor library.
@@ -373,6 +373,36 @@ const bfd_arch_info_type bfd_powerpc_archs[] =
     powerpc_compatible,
     bfd_default_scan,
     bfd_arch_default_fill,
+    &bfd_powerpc_archs[19]
+  },
+  {
+    64, /* 64 bits in a word */
+    64, /* 64 bits in an address */
+    8,  /* 8 bits in a byte */
+    bfd_arch_powerpc,
+    bfd_mach_ppc_e5500,
+    "powerpc",
+    "powerpc:e5500",
+    3,
+    FALSE, /* not the default */
+    powerpc_compatible,
+    bfd_default_scan,
+    bfd_arch_default_fill,
+    &bfd_powerpc_archs[20]
+  },
+  {
+    64, /* 64 bits in a word */
+    64, /* 64 bits in an address */
+    8,  /* 8 bits in a byte */
+    bfd_arch_powerpc,
+    bfd_mach_ppc_e6500,
+    "powerpc",
+    "powerpc:e6500",
+    3,
+    FALSE, /* not the default */
+    powerpc_compatible,
+    bfd_default_scan,
+    bfd_arch_default_fill,
     0
   }
 };

gas/ChangeLog

@@ -1,3 +1,10 @@
+2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
+
+	* config/tc-ppc.c (md_show_usage): Document -me5500 and -me6500.
+	(ppc_handle_align): Add termination nop opcode for e500mc family.
+	* doc/as.texinfo: Document options -me5500 and -me6500.
+	* doc/c-ppc.texi: Likewise.
+
 2012-03-07  Nick Clifton  <nickc@redhat.com>
 
 	* config/tc-mn10300.c (other_registers): Add SSP and USP.

gas/config/tc-ppc.c

@@ -1,6 +1,6 @@
 /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000)
    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-   2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
+   2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
    Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support.
 
@@ -1265,6 +1265,8 @@ PowerPC options:\n\
 -me500, -me500x2        generate code for Motorola e500 core complex\n\
 -me500mc,               generate code for Freescale e500mc core complex\n\
 -me500mc64,             generate code for Freescale e500mc64 core complex\n\
+-me5500,                generate code for Freescale e5500 core complex\n\
+-me6500,                generate code for Freescale e6500 core complex\n\
 -mspe                   generate code for Motorola SPE instructions\n\
 -mtitan                 generate code for AppliedMicro Titan core complex\n\
 -mregnames              Allow symbolic names for registers\n\
@@ -6014,8 +6016,14 @@ ppc_handle_align (struct frag *fragP)
 	    }
 
 	  if ((ppc_cpu & PPC_OPCODE_POWER7) != 0)
-	    /* power7 group terminating nop: "ori 2,2,0".  */
-	    md_number_to_chars (dest, 0x60420000, 4);
+	    {
+	      if (ppc_cpu & PPC_OPCODE_E500MC)
+		/* e500mc group terminating nop: "ori 0,0,0".  */
+		md_number_to_chars (dest, 0x60000000, 4);
+	      else
+		/* power7 group terminating nop: "ori 2,2,0".  */
+		md_number_to_chars (dest, 0x60420000, 4);
+	    }
 	  else
 	    /* power6 group terminating nop: "ori 1,1,0".  */
 	    md_number_to_chars (dest, 0x60210000, 4);

gas/doc/as.texinfo

@@ -1,6 +1,6 @@
 \input texinfo @c                               -*-Texinfo-*-
 @c  Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-@c  2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
+@c  2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
 @c  Free Software Foundation, Inc.
 @c UPDATE!!  On future updates--
 @c   (1)   check for new machine-dep cmdline options in
@@ -439,8 +439,8 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-a32}|@b{-a64}]
    [@b{-mpwrx}|@b{-mpwr2}|@b{-mpwr}|@b{-m601}|@b{-mppc}|@b{-mppc32}|@b{-m603}|@b{-m604}|@b{-m403}|@b{-m405}|
     @b{-m440}|@b{-m464}|@b{-m476}|@b{-m7400}|@b{-m7410}|@b{-m7450}|@b{-m7455}|@b{-m750cl}|@b{-mppc64}|
-    @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-mppc64bridge}|@b{-mbooke}|
-    @b{-mpower4}|@b{-mpr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}|
+    @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|@b{-me6500}|@b{-mppc64bridge}|
+    @b{-mbooke}|@b{-mpower4}|@b{-mpr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}|
     @b{-mpower7}|@b{-mpw7}|@b{-ma2}|@b{-mcell}|@b{-mspe}|@b{-mtitan}|@b{-me300}|@b{-mcom}]
    [@b{-many}] [@b{-maltivec}|@b{-mvsx}]
    [@b{-mregnames}|@b{-mno-regnames}]

gas/doc/c-ppc.texi

@@ -1,5 +1,5 @@
 @c Copyright 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011
-@c Free Software Foundation, Inc.
+@c 2012 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @c man end
@@ -88,6 +88,12 @@ Generate code for Freescale e500mc core complex.
 @item -me500mc64
 Generate code for Freescale e500mc64 core complex.
 
+@item -me5500
+Generate code for Freescale e5500 core complex.
+
+@item -me6500
+Generate code for Freescale e6500 core complex.
+
 @item -mspe
 Generate code for Motorola SPE instructions.
 

gas/testsuite/ChangeLog

@@ -1,3 +1,16 @@
+2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
+
+	* gas/ppc/e500mc64_nop.s: New test case for e500mc family
+	termination nops.
+	* gas/ppc/e500mc64_nop.d: Likewise.
+	* gas/ppc/e5500_nop.s: Likewise.
+	* gas/ppc/e5500_nop.d: Likewise.
+	* gas/ppc/e6500_nop.s: Likewise.
+	* gas/ppc/e6500_nop.d: Likewise.
+	* gas/ppc/e6500.s: New.
+	* gas/ppc/e6500.d: Likewise.
+	* gas/ppc/ppc.exp: Run e6500, e500mc64_nop, e5500_nop, and e6500_nop.
+
 2012-03-08  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 
 	* gas/s390/esa-g5.d: Move length field to the second operand.

gas/testsuite/gas/ppc/e500mc64_nop.d

@@ -0,0 +1,13 @@
+#as: -mppc -me500mc64
+#objdump: -dr -Me500mc64
+#name: Power E500MC64 nop tests
+
+.*: +file format elf(32)?(64)?-powerpc.*
+
+Disassembly of section \.text:
+
+0+00 <start>:
+   0:	60 00 00 00 	nop
+   4:	60 00 00 00 	nop
+   8:	60 00 00 00 	nop
+   c:	60 00 00 00 	nop

gas/testsuite/gas/ppc/e500mc64_nop.s

@@ -0,0 +1,5 @@
+# Power E500MC64 nop tests
+	.section  ".text"
+start:
+	nop
+	.p2align 4,,15

gas/testsuite/gas/ppc/e5500_nop.d

@@ -0,0 +1,13 @@
+#as: -mppc -me5500
+#objdump: -dr -Me5500
+#name: Power E5500 nop tests
+
+.*: +file format elf(32)?(64)?-powerpc.*
+
+Disassembly of section \.text:
+
+0+00 <start>:
+   0:	60 00 00 00 	nop
+   4:	60 00 00 00 	nop
+   8:	60 00 00 00 	nop
+   c:	60 00 00 00 	nop

gas/testsuite/gas/ppc/e5500_nop.s

@@ -0,0 +1,5 @@
+# Power E5500 nop tests
+	.section  ".text"
+start:
+	nop
+	.p2align 4,,15

gas/testsuite/gas/ppc/e6500.d

@@ -0,0 +1,75 @@
+#as: -mppc -me6500
+#objdump: -dr -Me6500
+#name: Power E6500 tests
+
+.*: +file format elf(32)?(64)?-powerpc.*
+
+Disassembly of section \.text:
+
+0+00 <start>:
+   0:	10 01 10 c0 	vabsdub v0,v1,v2
+   4:	10 01 11 00 	vabsduh v0,v1,v2
+   8:	10 01 11 40 	vabsduw v0,v1,v2
+   c:	7c 01 10 dc 	mvidsplt v0,r1,r2
+  10:	7c 01 11 1c 	mviwsplt v0,r1,r2
+  14:	7c 00 12 0a 	lvexbx  v0,0,r2
+  18:	7c 01 12 0a 	lvexbx  v0,r1,r2
+  1c:	7c 00 12 4a 	lvexhx  v0,0,r2
+  20:	7c 01 12 4a 	lvexhx  v0,r1,r2
+  24:	7c 00 12 8a 	lvexwx  v0,0,r2
+  28:	7c 01 12 8a 	lvexwx  v0,r1,r2
+  2c:	7c 00 13 0a 	stvexbx v0,0,r2
+  30:	7c 01 13 0a 	stvexbx v0,r1,r2
+  34:	7c 00 13 4a 	stvexhx v0,0,r2
+  38:	7c 01 13 4a 	stvexhx v0,r1,r2
+  3c:	7c 00 13 8a 	stvexwx v0,0,r2
+  40:	7c 01 13 8a 	stvexwx v0,r1,r2
+  44:	7c 00 12 4e 	lvepx   v0,0,r2
+  48:	7c 01 12 4e 	lvepx   v0,r1,r2
+  4c:	7c 00 12 0e 	lvepxl  v0,0,r2
+  50:	7c 01 12 0e 	lvepxl  v0,r1,r2
+  54:	7c 00 16 4e 	stvepx  v0,0,r2
+  58:	7c 01 16 4e 	stvepx  v0,r1,r2
+  5c:	7c 00 16 0e 	stvepxl v0,0,r2
+  60:	7c 01 16 0e 	stvepxl v0,r1,r2
+  64:	7c 00 14 8a 	lvtlx   v0,0,r2
+  68:	7c 01 14 8a 	lvtlx   v0,r1,r2
+  6c:	7c 00 16 8a 	lvtlxl  v0,0,r2
+  70:	7c 01 16 8a 	lvtlxl  v0,r1,r2
+  74:	7c 00 14 4a 	lvtrx   v0,0,r2
+  78:	7c 01 14 4a 	lvtrx   v0,r1,r2
+  7c:	7c 00 16 4a 	lvtrxl  v0,0,r2
+  80:	7c 01 16 4a 	lvtrxl  v0,r1,r2
+  84:	7c 00 15 8a 	stvflx  v0,0,r2
+  88:	7c 01 15 8a 	stvflx  v0,r1,r2
+  8c:	7c 00 17 8a 	stvflxl v0,0,r2
+  90:	7c 01 17 8a 	stvflxl v0,r1,r2
+  94:	7c 00 15 4a 	stvfrx  v0,0,r2
+  98:	7c 01 15 4a 	stvfrx  v0,r1,r2
+  9c:	7c 00 17 4a 	stvfrxl v0,0,r2
+  a0:	7c 01 17 4a 	stvfrxl v0,r1,r2
+  a4:	7c 00 14 ca 	lvswx   v0,0,r2
+  a8:	7c 01 14 ca 	lvswx   v0,r1,r2
+  ac:	7c 00 16 ca 	lvswxl  v0,0,r2
+  b0:	7c 01 16 ca 	lvswxl  v0,r1,r2
+  b4:	7c 00 15 ca 	stvswx  v0,0,r2
+  b8:	7c 01 15 ca 	stvswx  v0,r1,r2
+  bc:	7c 00 17 ca 	stvswxl v0,0,r2
+  c0:	7c 01 17 ca 	stvswxl v0,r1,r2
+  c4:	7c 00 16 0a 	lvsm    v0,0,r2
+  c8:	7c 01 16 0a 	lvsm    v0,r1,r2
+  cc:	7f 5a d3 78 	miso
+  d0:	7c 00 04 ac 	sync    
+  d4:	7c 00 04 ac 	sync    
+  d8:	7c 20 04 ac 	lwsync
+  dc:	7c 00 04 ac 	sync    
+  e0:	7c 07 04 ac 	sync    0,7
+  e4:	7c 28 04 ac 	sync    1,8
+  e8:	7c 00 00 c3 	dni     0,0
+  ec:	7f ff 00 c3 	dni     31,31
+  f0:	7c 40 0b 4d 	dcblq.  2,0,r1
+  f4:	7c 43 0b 4d 	dcblq.  2,r3,r1
+  f8:	7c 40 09 8d 	icblq.  2,0,r1
+  fc:	7c 43 09 8d 	icblq.  2,r3,r1
+ 100:	7c 10 02 dc 	mftmr   r0,16
+ 104:	7c 10 03 dc 	mttmr   16,r0

gas/testsuite/gas/ppc/e6500.s

@@ -0,0 +1,69 @@
+# Power E6500 tests
+	.section ".text"
+start:
+	vabsdub	0, 1, 2
+	vabsduh	0, 1, 2
+	vabsduw	0, 1, 2
+	mvidsplt 0, 1, 2
+	mviwsplt 0, 1, 2
+	lvexbx	0, 0, 2
+	lvexbx	0, 1, 2
+	lvexhx	0, 0, 2
+	lvexhx	0, 1, 2
+	lvexwx	0, 0, 2
+	lvexwx	0, 1, 2
+	stvexbx	0, 0, 2
+	stvexbx	0, 1, 2
+	stvexhx	0, 0, 2
+	stvexhx	0, 1, 2
+	stvexwx	0, 0, 2
+	stvexwx	0, 1, 2
+	lvepx	0, 0, 2
+	lvepx	0, 1, 2
+	lvepxl	0, 0, 2
+	lvepxl	0, 1, 2
+	stvepx	0, 0, 2
+	stvepx	0, 1, 2
+	stvepxl	0, 0, 2
+	stvepxl	0, 1, 2
+	lvtlx	0, 0, 2
+	lvtlx	0, 1, 2
+	lvtlxl	0, 0, 2
+	lvtlxl	0, 1, 2
+	lvtrx	0, 0, 2
+	lvtrx	0, 1, 2
+	lvtrxl	0, 0, 2
+	lvtrxl	0, 1, 2
+	stvflx	0, 0, 2
+	stvflx	0, 1, 2
+	stvflxl	0, 0, 2
+	stvflxl	0, 1, 2
+	stvfrx	0, 0, 2
+	stvfrx	0, 1, 2
+	stvfrxl	0, 0, 2
+	stvfrxl	0, 1, 2
+	lvswx	0, 0, 2
+	lvswx	0, 1, 2
+	lvswxl	0, 0, 2
+	lvswxl	0, 1, 2
+	stvswx	0, 0, 2
+	stvswx	0, 1, 2
+	stvswxl	0, 0, 2
+	stvswxl	0, 1, 2
+	lvsm	0, 0, 2
+	lvsm	0, 1, 2
+	miso
+	sync
+	sync	0,0
+	sync	1,0
+	sync	2,0
+	sync	3,7
+	sync	3,8
+	dni	0,0
+	dni	31,31
+	dcblq.	2,0,1
+	dcblq.	2,3,1
+	icblq.	2,0,1
+	icblq.	2,3,1
+	mftmr	0,16
+	mttmr	16,0

gas/testsuite/gas/ppc/e6500_nop.d

@@ -0,0 +1,13 @@
+#as: -mppc -me6500
+#objdump: -dr -Me6500
+#name: Power E6500 nop tests
+
+.*: +file format elf(32)?(64)?-powerpc.*
+
+Disassembly of section \.text:
+
+0+00 <start>:
+   0:	60 00 00 00 	nop
+   4:	60 00 00 00 	nop
+   8:	60 00 00 00 	nop
+   c:	60 00 00 00 	nop

gas/testsuite/gas/ppc/e6500_nop.s

@@ -0,0 +1,5 @@
+# Power E6500 nop tests
+	.section  ".text"
+start:
+	nop
+	.p2align 4,,15