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Merged
merged 4 commits into from
May 15, 2025
Merged

Add additional serial link for dram #33

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8b4cf8b
Add additional serial link for dram
micprog May 14, 2025
f64eadc
Fix format
micprog May 14, 2025
96aa07b
Bump PD reference
micprog May 15, 2025
34e81f9
Fix PD update
micprog May 15, 2025
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2 changes: 1 addition & 1 deletion Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -97,7 +97,7 @@ floo-clean:
###################

PD_REMOTE ?= git@iis-git.ee.ethz.ch:picobello/picobello-pd.git
PD_COMMIT ?= cf2aeacec6776f598b76de8638fe809729e35d96
PD_COMMIT ?= 1c0dd5204bd517cf0d16f7a7169220a06d544443
PD_DIR = $(PB_ROOT)/pd

.PHONY: init-pd clean-pd
Expand Down
102 changes: 86 additions & 16 deletions hw/cheshire_tile.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -64,6 +64,11 @@ module cheshire_tile
output logic [SlinkNumChan-1:0] slink_rcv_clk_o,
input logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i,
output logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o,
// DRAM Serial link interface
input logic [SlinkNumChan-1:0] dram_slink_rcv_clk_i,
output logic [SlinkNumChan-1:0] dram_slink_rcv_clk_o,
input logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] dram_slink_i,
output logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] dram_slink_o,
// Chimney ports
input id_t id_i,
// Router ports
Expand Down Expand Up @@ -226,15 +231,19 @@ module cheshire_tile

`CHESHIRE_TYPEDEF_ALL(csh_, CheshireCfg)

csh_axi_mst_req_t axi_ext_mst_req_in;
csh_axi_mst_rsp_t axi_ext_mst_rsp_out;
csh_axi_slv_req_t axi_ext_slv_req_out;
csh_axi_slv_rsp_t axi_ext_slv_rsp_in;
csh_axi_llc_req_t axi_llc_req;
csh_axi_llc_rsp_t axi_llc_rsp;
csh_axi_mst_req_t [CheshireCfg.AxiExtNumMst-1:0] axi_ext_mst_req_in;
csh_axi_mst_rsp_t [CheshireCfg.AxiExtNumMst-1:0] axi_ext_mst_rsp_out;
csh_axi_slv_req_t [CheshireCfg.AxiExtNumSlv-1:0] axi_ext_slv_req_out;
csh_axi_slv_rsp_t [CheshireCfg.AxiExtNumSlv-1:0] axi_ext_slv_rsp_in;
csh_reg_req_t [CheshireCfg.RegExtNumSlv-1:0] reg_ext_req;
csh_reg_rsp_t [CheshireCfg.RegExtNumSlv-1:0] reg_ext_rsp;

`AXI_ASSIGN_REQ_STRUCT(axi_ext_mst_req_in, nw_join_req)
`AXI_ASSIGN_RESP_STRUCT(nw_join_rsp, axi_ext_mst_rsp_out)
`AXI_ASSIGN_REQ_STRUCT(narrow_in_req, axi_ext_slv_req_out)
`AXI_ASSIGN_RESP_STRUCT(axi_ext_slv_rsp_in, narrow_in_rsp)
`AXI_ASSIGN_REQ_STRUCT(axi_ext_mst_req_in[0], nw_join_req)
`AXI_ASSIGN_RESP_STRUCT(nw_join_rsp, axi_ext_mst_rsp_out[0])
`AXI_ASSIGN_REQ_STRUCT(narrow_in_req, axi_ext_slv_req_out[0])
`AXI_ASSIGN_RESP_STRUCT(axi_ext_slv_rsp_in[0], narrow_in_rsp)

cheshire_soc #(
.Cfg (CheshireCfg),
Expand All @@ -252,16 +261,14 @@ module cheshire_tile
.test_mode_i,
.boot_mode_i,
.rtc_i,
// TODO(fischeti): Connect if we will use DRAM/Hyperram
.axi_llc_mst_req_o(),
.axi_llc_mst_rsp_i('0),
.axi_llc_mst_req_o(axi_llc_req),
.axi_llc_mst_rsp_i(axi_llc_rsp),
.axi_ext_mst_req_i(axi_ext_mst_req_in),
.axi_ext_mst_rsp_o(axi_ext_mst_rsp_out),
.axi_ext_slv_req_o(axi_ext_slv_req_out),
.axi_ext_slv_rsp_i(axi_ext_slv_rsp_in),
// TODO(fischeti): Connect to SoC config registers if needed
.reg_ext_slv_req_o(),
.reg_ext_slv_rsp_i('0),
.reg_ext_slv_req_o(reg_ext_req),
.reg_ext_slv_rsp_i(reg_ext_rsp),
// TODO(fischeti): Do we need external interrupts?
.intr_ext_i ('0),
.intr_ext_o (),
Expand Down Expand Up @@ -306,13 +313,13 @@ module cheshire_tile
.slink_rcv_clk_o,
.slink_i,
.slink_o,
// TODO(fischeti): Check if we need/want VGA
// We do not need/want VGA
.vga_hsync_o (),
.vga_vsync_o (),
.vga_red_o (),
.vga_green_o (),
.vga_blue_o (),
// TODO(fischeti): Check if we need/want USB
// We do not need/want USB
.usb_clk_i ('0),
.usb_rst_ni ('0),
.usb_dm_i ('0),
Expand All @@ -323,4 +330,67 @@ module cheshire_tile
.usb_dp_oe_o ()
);

// Serial Link to connect to DRAM on an FPGA

csh_axi_llc_req_t dram_slink_err_req;
csh_axi_llc_rsp_t dram_slink_err_rsp;

serial_link #(
.axi_req_t (csh_axi_llc_req_t),
.axi_rsp_t (csh_axi_llc_rsp_t),
.cfg_req_t (csh_reg_req_t),
.cfg_rsp_t (csh_reg_rsp_t),
.aw_chan_t (csh_axi_llc_aw_chan_t),
.ar_chan_t (csh_axi_llc_ar_chan_t),
.r_chan_t (csh_axi_llc_r_chan_t),
.w_chan_t (csh_axi_llc_w_chan_t),
.b_chan_t (csh_axi_llc_b_chan_t),
.hw2reg_t (serial_link_single_channel_reg_pkg::serial_link_single_channel_hw2reg_t),
.reg2hw_t (serial_link_single_channel_reg_pkg::serial_link_single_channel_reg2hw_t),
.NumChannels(SlinkNumChan),
.NumLanes (SlinkNumLanes),
.MaxClkDiv (SlinkMaxClkDiv)
) i_dram_serial_link (
.clk_i,
.rst_ni,
.clk_sl_i (clk_i),
.rst_sl_ni (rst_ni),
.clk_reg_i (clk_i),
.rst_reg_ni (rst_ni),
.testmode_i (test_mode_i),
.axi_in_req_i (axi_llc_req),
.axi_in_rsp_o (axi_llc_rsp),
.axi_out_req_o(dram_slink_err_req),
.axi_out_rsp_i(dram_slink_err_rsp),
.cfg_req_i (reg_ext_req[CshRegExtDramSerialLink]),
.cfg_rsp_o (reg_ext_rsp[CshRegExtDramSerialLink]),
.ddr_rcv_clk_i(dram_slink_rcv_clk_i),
.ddr_rcv_clk_o(dram_slink_rcv_clk_o),
.ddr_i (dram_slink_i),
.ddr_o (dram_slink_o),
.isolated_i ('0),
.isolate_o (),
.clk_ena_o (),
.reset_no ()
);

axi_err_slv #(
.AxiIdWidth(CheshireCfg.AxiMstIdWidth + $clog2(
csh_axi__AxiIn.num_in
) + CheshireCfg.LlcNotBypass),
.axi_req_t(csh_axi_llc_req_t),
.axi_resp_t(csh_axi_llc_rsp_t),
.Resp(axi_pkg::RESP_DECERR),
.RespWidth(CheshireCfg.AxiDataWidth),
.RespData(64'hCA11AB1EBADCAB1E),
.ATOPs(1'b1),
.MaxTrans(4) // TODO maybe tune, but this block should never be used.
) i_dram_slink_err (
.clk_i,
.rst_ni,
.test_i (test_mode_i),
.slv_req_i (dram_slink_err_req),
.slv_resp_o(dram_slink_err_rsp)
);

endmodule
12 changes: 10 additions & 2 deletions hw/picobello_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -106,16 +106,24 @@ package picobello_pkg;
// Cheshire //
////////////////

localparam int unsigned CshRegExtDramSerialLink = 0;
localparam int unsigned CshNumRegExt = 1;

// Define function to derive configuration from Cheshire defaults.
function automatic cheshire_pkg::cheshire_cfg_t gen_cheshire_cfg();
cheshire_pkg::cheshire_cfg_t ret = cheshire_pkg::DefaultCfg;
// Enable the external AXI master and slave interfaces
ret.AxiExtNumMst = 1;
ret.AxiExtNumSlv = 1;
ret.AxiExtNumRules = 1;
ret.RegExtNumSlv = CshNumRegExt;
ret.RegExtNumRules = CshNumRegExt;
ret.AxiExtRegionIdx[0] = 0;
ret.AxiExtRegionStart[0] = 'h2000_0000;
ret.AxiExtRegionEnd[0] = 'h8000_0000;
ret.RegExtRegionIdx[0] = CshRegExtDramSerialLink;
ret.RegExtRegionStart[0] = 'h3100_0000;
ret.RegExtRegionEnd[0] = 'h3100_1000;
// TODO(fischeti): Currently, I don't see a reason to have a CIE region
// Which is why we just put the CIE region after the on-chip region for now
ret.Cva6ExtCieOnTop = 1;
Expand All @@ -126,9 +134,9 @@ package picobello_pkg;
ret.AxiMstIdWidth = aw_bt'(max(AxiCfgN.OutIdWidth, AxiCfgW.OutIdWidth));
// TODO(fischeti): Check if we need external interrupts for each hart/cluster
ret.NumExtIrqHarts = doub_bt'(NumClusters);
// TODO(fischeti): Check if we need/want VGA
// We do not need/want VGA
ret.Vga = 1'b0;
// TODO(fischeti): Check if we need/want USB
// We do not need/want USB
ret.Usb = 1'b0;
// TODO(fischeti): Check if we need/want an AXI to DRAM
ret.LlcOutRegionStart = 'h8000_0000;
Expand Down
11 changes: 10 additions & 1 deletion hw/picobello_top.sv
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Expand Up @@ -56,7 +56,12 @@ module picobello_top
input logic [SlinkNumChan-1:0] slink_rcv_clk_i,
output logic [SlinkNumChan-1:0] slink_rcv_clk_o,
input logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i,
output logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o
output logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o,
// DRAM Serial link interface
input logic [SlinkNumChan-1:0] dram_slink_rcv_clk_i,
output logic [SlinkNumChan-1:0] dram_slink_rcv_clk_o,
input logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] dram_slink_i,
output logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] dram_slink_o
);

floo_req_t [MeshDim.x-1:0][MeshDim.y-1:0][West:North] floo_req_in, floo_req_out;
Expand Down Expand Up @@ -158,6 +163,10 @@ module picobello_top
.slink_rcv_clk_o,
.slink_i,
.slink_o,
.dram_slink_rcv_clk_i,
.dram_slink_rcv_clk_o,
.dram_slink_i,
.dram_slink_o,
.id_i (CheshireId),
.floo_req_o (floo_req_out[CheshireId.x][CheshireId.y]),
.floo_rsp_i (floo_rsp_in[CheshireId.x][CheshireId.y]),
Expand Down
87 changes: 48 additions & 39 deletions target/sim/src/fixture_picobello_top.sv
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Expand Up @@ -55,48 +55,57 @@ module fixture_picobello_top;
logic [SlinkNumChan-1:0] slink_rcv_clk_o;
logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i;
logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o;

logic [SlinkNumChan-1:0] dram_slink_rcv_clk_i;
logic [SlinkNumChan-1:0] dram_slink_rcv_clk_o;
logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] dram_slink_i;
logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] dram_slink_o;
// verilog_format: on

picobello_top dut (
.clk_i (clk),
.rst_ni (rst_n),
.test_mode_i (test_mode),
.boot_mode_i (boot_mode),
.rtc_i (rtc),
.jtag_tck_i (jtag_tck),
.jtag_trst_ni (jtag_trst_n),
.jtag_tms_i (jtag_tms),
.jtag_tdi_i (jtag_tdi),
.jtag_tdo_o (jtag_tdo),
.jtag_tdo_oe_o (),
.uart_tx_o (uart_tx),
.uart_rx_i (uart_rx),
.uart_rts_no (),
.uart_dtr_no (),
.uart_cts_ni (1'b0),
.uart_dsr_ni (1'b0),
.uart_dcd_ni (1'b0),
.uart_rin_ni (1'b0),
.i2c_sda_o (i2c_sda_o),
.i2c_sda_i (i2c_sda_i),
.i2c_sda_en_o (i2c_sda_en),
.i2c_scl_o (i2c_scl_o),
.i2c_scl_i (i2c_scl_i),
.i2c_scl_en_o (i2c_scl_en),
.spih_sck_o (spih_sck_o),
.spih_sck_en_o (spih_sck_en),
.spih_csb_o (spih_csb_o),
.spih_csb_en_o (spih_csb_en),
.spih_sd_o (spih_sd_o),
.spih_sd_en_o (spih_sd_en),
.spih_sd_i (spih_sd_i),
.gpio_i ('0),
.gpio_o (),
.gpio_en_o (),
.slink_rcv_clk_i(slink_rcv_clk_i),
.slink_rcv_clk_o(slink_rcv_clk_o),
.slink_i (slink_i),
.slink_o (slink_o)
.clk_i (clk),
.rst_ni (rst_n),
.test_mode_i (test_mode),
.boot_mode_i (boot_mode),
.rtc_i (rtc),
.jtag_tck_i (jtag_tck),
.jtag_trst_ni (jtag_trst_n),
.jtag_tms_i (jtag_tms),
.jtag_tdi_i (jtag_tdi),
.jtag_tdo_o (jtag_tdo),
.jtag_tdo_oe_o (),
.uart_tx_o (uart_tx),
.uart_rx_i (uart_rx),
.uart_rts_no (),
.uart_dtr_no (),
.uart_cts_ni (1'b0),
.uart_dsr_ni (1'b0),
.uart_dcd_ni (1'b0),
.uart_rin_ni (1'b0),
.i2c_sda_o (i2c_sda_o),
.i2c_sda_i (i2c_sda_i),
.i2c_sda_en_o (i2c_sda_en),
.i2c_scl_o (i2c_scl_o),
.i2c_scl_i (i2c_scl_i),
.i2c_scl_en_o (i2c_scl_en),
.spih_sck_o (spih_sck_o),
.spih_sck_en_o (spih_sck_en),
.spih_csb_o (spih_csb_o),
.spih_csb_en_o (spih_csb_en),
.spih_sd_o (spih_sd_o),
.spih_sd_en_o (spih_sd_en),
.spih_sd_i (spih_sd_i),
.gpio_i ('0),
.gpio_o (),
.gpio_en_o (),
.slink_rcv_clk_i (slink_rcv_clk_i),
.slink_rcv_clk_o (slink_rcv_clk_o),
.slink_i (slink_i),
.slink_o (slink_o),
.dram_slink_rcv_clk_i(dram_slink_rcv_clk_i),
.dram_slink_rcv_clk_o(dram_slink_rcv_clk_o),
.dram_slink_i (dram_slink_i),
.dram_slink_o (dram_slink_o)
);

////////////////////////
Expand Down