hw: Add multicast support

.gitignore

@@ -10,6 +10,9 @@
 # Python virtual environment
 .venv
 
+# Emacs undo tree
+*undo-tree*
+
 # Generated source files
 .generated
 

Bender.lock

@@ -15,10 +15,10 @@ packages:
     - apb
     - register_interface
   axi:
-    revision: 39f5f2d51c5e524f6fc5cf8b6e901f7dcc5622d7
-    version: 0.39.6
+    revision: bec548fa2a9b18cbd7531105bb1fdf481ea8ad49
+    version: null
     source:
-      Git: https://github.com/pulp-platform/axi.git
+      Git: https://github.com/colluca/axi.git
     dependencies:
     - common_cells
     - common_verification
@@ -129,8 +129,8 @@ packages:
     - scm
     - tech_cells_generic
   common_cells:
-    revision: 9afda9abb565971649c2aa0985639c096f351171
-    version: 1.38.0
+    revision: 0fd2ba32926c0360534dc3d5795143cb259abb1c
+    version: null
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
@@ -166,8 +166,8 @@ packages:
       Path: deps/fhg_spu_cluster
     dependencies: []
   floo_noc:
-    revision: 6ac187326b222a491180cc3f77e0e4e5a69f5167
-    version: 0.6.1
+    revision: a86e8b307d147e567ea3c8da924b774a7f15e08b
+    version: null
     source:
       Git: https://github.com/pulp-platform/FlooNoC.git
     dependencies:
@@ -192,8 +192,8 @@ packages:
     dependencies:
     - common_cells
   idma:
-    revision: ff5d56fffb3767814db88d6bf8f381974ea33aa5
-    version: 0.6.4
+    revision: 5ccd718224ad76f2d0ce5fe512ad6c5e47c71844
+    version: null
     source:
       Git: https://github.com/pulp-platform/iDMA.git
     dependencies:
@@ -270,10 +270,10 @@ packages:
     - common_cells
     - register_interface
   snitch_cluster:
-    revision: b60f5574053ba1a808d4547a31be14efee1c0e39
+    revision: 03ef4285322df422e32d06a1116d4ddde8bccd23
     version: null
     source:
-      Git: https://github.com/pulp-platform/snitch_cluster.git
+      Git: https://github.com/Lore0599/snitch_cluster.git
     dependencies:
     - axi
     - axi_riscv_atomics

Bender.yml

@@ -12,8 +12,8 @@ dependencies:
   axi: { git: "https://github.com/pulp-platform/axi.git", version: "0.39.6" }
   common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: "1.37.0" }
   cheshire: { git: "https://github.com/pulp-platform/cheshire.git", rev: "main" }
-  floo_noc: { git: "https://github.com/pulp-platform/FlooNoC.git", version: "0.6.1"}
-  snitch_cluster: { git: "https://github.com/pulp-platform/snitch_cluster.git", rev: "main" }
+  snitch_cluster:  { git: "https://github.com/Lore0599/snitch_cluster.git", rev: "multicast-integration" }
+  floo_noc: { git: "https://github.com/pulp-platform/FlooNoC.git", rev: "fischeti/new-mcast"}
   obi: { git: "https://github.com/pulp-platform/obi.git", rev: "ad1d48f025be540344960ea83b4bff39876f9b36"}
   axi_obi: { path: "hw/axi_obi" }
   picobello-pd:  { path: "./pd" }

cfg/mcast_snitch_cluster.hjson

@@ -0,0 +1,139 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Cluster configuration for a simple testbench system.
+{
+    nr_clusters: 4,
+    cluster: {
+        cluster_base_addr: 0x20000000,
+        cluster_base_offset: 0x40000,
+        cluster_base_hartid: 0,
+        addr_width: 48,
+        data_width: 64,
+        atomic_id_width: 3, // clog2(total number of clusters)
+        user_width: 51, // addr_width + atomic_id_width
+        tcdm: {
+            size: 128,
+            banks: 32,
+        },
+        cluster_periph_size: 60, // kB
+        zero_mem_size: 64, // kB
+        dma_data_width: 512,
+        dma_axi_req_fifo_depth: 3,
+        dma_req_fifo_depth: 3,
+        narrow_trans: 4,
+        wide_trans: 32,
+        dma_user_width: 48,
+        enable_multicast: true,
+        cluster_base_expose: true,
+        alias_region_enable: true,
+        alias_region_base: 0x28000000,
+        // TODO(fischeti): Check if we need Snitch VM support
+        vm_support: false,
+        // Timing parameters
+        timing: {
+            lat_comp_fp32: 2,
+            lat_comp_fp64: 3,
+            lat_comp_fp16: 1,
+            lat_comp_fp16_alt: 1,
+            lat_comp_fp8: 1,
+            lat_comp_fp8_alt: 1,
+            lat_noncomp: 1,
+            lat_conv: 1,
+            lat_sdotp: 3,
+            fpu_pipe_config: "BEFORE",
+            narrow_xbar_latency: "CUT_ALL_PORTS",
+            wide_xbar_latency: "CUT_ALL_PORTS",
+            // Isolate the core.
+            register_core_req: true,
+            register_core_rsp: true,
+            register_offload_req: true,
+            register_offload_rsp: true
+        },
+        hives: [
+            // Hive 0
+            {
+                icache: {
+                    size: 8, // total instruction cache size in kByte
+                    ways: 2, // number of ways
+                    cacheline: 256 // word size in bits
+                },
+                cores: [
+                    { $ref: "#/compute_core_template" },
+                    { $ref: "#/compute_core_template" },
+                    { $ref: "#/compute_core_template" },
+                    { $ref: "#/compute_core_template" },
+                    { $ref: "#/compute_core_template" },
+                    { $ref: "#/compute_core_template" },
+                    { $ref: "#/compute_core_template" },
+                    { $ref: "#/compute_core_template" },
+                    { $ref: "#/dma_core_template" },
+                ]
+            }
+        ]
+    },
+    external_addr_regions: [
+        {
+            name: "l2spm",
+            address: 0x30000000,
+            length: 0x10000000,
+            cacheable: true
+        },
+        {
+            name: "dram",
+            address: 0x80000000,
+            length: 0x80000000
+        },
+        {
+            name: "clint",
+            address: 0xffff0000,
+            length: 0x00001000
+        }
+    ],
+    // Templates.
+    compute_core_template: {
+        isa: "rv32imafd",
+        xssr: true,
+        xfrep: true,
+        xdma: false,
+        xf16: true,
+        xf16alt: true,
+        xf8: true,
+        xf8alt: true,
+        xfdotp: true,
+        xfvec: true,
+        num_int_outstanding_loads: 1,
+        num_int_outstanding_mem: 4,
+        num_fp_outstanding_loads: 4,
+        num_fp_outstanding_mem: 4,
+        num_sequencer_instructions: 16,
+        num_dtlb_entries: 1,
+        num_itlb_entries: 1,
+        // Enable division/square root unit
+        // TODO(fischeti): Do we need a division/square root unit?
+        // Xdiv_sqrt: true,
+        // TODO(fischeti): Do we want SSR indirection support?
+    },
+    dma_core_template: {
+        isa: "rv32imafd",
+        // Xdiv_sqrt: true,
+        // isa: "rv32ema",
+        xdma: true,
+        xssr: false,
+        xfrep: false,
+        xf16: false,
+        xf16alt: false,
+        xf8: false,
+        xf8alt: false,
+        xfdotp: false,
+        xfvec: false,
+        num_int_outstanding_loads: 1,
+        num_int_outstanding_mem: 4,
+        num_fp_outstanding_loads: 4,
+        num_fp_outstanding_mem: 4,
+        num_sequencer_instructions: 16,
+        num_dtlb_entries: 1,
+        num_itlb_entries: 1,
+    }
+}

cfg/mini_picobello_noc.yml

@@ -9,6 +9,7 @@ network_type: "narrow-wide"
 routing:
   route_algo: "XY"
   use_id_table: true
+  en_multicast: true
 
 protocols:
   - name: "narrow_in"

cfg/snitch_cluster.json

@@ -8,10 +8,11 @@
     cluster: {
         cluster_base_addr: 0x20000000,
         cluster_base_offset: 0x40000,
-        cluster_base_hartid: 0,
+        cluster_base_hartid: 1,
         addr_width: 48,
         data_width: 64,
-        user_width: 3, // clog2(nr_clusters + 1)
+        atomic_id_width: 4, // clog2(total number of clusters)
+        user_width: 51, // clog2(nr_clusters + 1)
         tcdm: {
             size: 128,
             banks: 32,
@@ -23,6 +24,8 @@
         dma_req_fifo_depth: 3,
         narrow_trans: 4,
         wide_trans: 32,
+        dma_user_width: 48,
+        enable_multicast: true,
         cluster_base_expose: true,
         alias_region_enable: true,
         alias_region_base: 0x28000000,

hw/cheshire_tile.sv

@@ -91,7 +91,7 @@ module cheshire_tile
   floo_nw_router #(
     .AxiCfgN     (AxiCfgN),
     .AxiCfgW     (AxiCfgW),
-    .RouteAlgo   (RouteCfg.RouteAlgo),
+    .RouteAlgo   (RouteCfg_NoMcast.RouteAlgo),
     .NumRoutes   (5),
     .InFifoDepth (2),
     .OutFifoDepth(2),
@@ -140,7 +140,7 @@ module cheshire_tile
     .AxiCfgW             (AxiCfgW),
     .ChimneyCfgN         (ChimneyCfgN),
     .ChimneyCfgW         (ChimneyCfgW),
-    .RouteCfg            (RouteCfg),
+    .RouteCfg            (RouteCfg_NoMcast),
     .AtopSupport         (1'b1),
     .MaxAtomicTxns       (AxiCfgN.OutIdWidth - 1),
     .Sam                 (Sam),