treewide: Change address range of L2, alias region & DRAM

Makefile

@@ -94,7 +94,7 @@ floo-clean:
 ###################
 
 PD_REMOTE ?= git@iis-git.ee.ethz.ch:picobello/picobello-pd.git
-PD_COMMIT ?= e1e618a872a631567dcc963eb3c987422eef4dbc
+PD_COMMIT ?= 1f60bc7569ec29e05ba996f7d7664476ac6771e2
 PD_DIR = $(PB_ROOT)/pd
 SPU_REMOTE ?= git@iis-git.ee.ethz.ch:picobello/fhg_spu_cluster.git
 SPU_COMMIT ?= 52ff92b99d07f7fa48d9b81c5d713c369bd4faa6

cfg/mini_picobello_noc.yml

@@ -58,7 +58,7 @@ endpoints:
         end: 0x2000_0000
         desc: "internal"
       - start: 0x8000_0000
-        end: 0x2_0000_0000
+        end: 0x200_0000_0000
         desc: "external"
     mgr_port_protocol:
       - "narrow_in"
@@ -68,7 +68,7 @@ endpoints:
   - name: "l2_spm"
     array: [1]
     addr_range:
-      base: 0x3000_0000
+      base: 0x7000_0000
       size: 0x0010_0000
     sbr_port_protocol:
       - "narrow_out"

cfg/picobello_noc.yml

@@ -58,7 +58,7 @@ endpoints:
         end: 0x2000_0000
         desc: "internal"
       - start: 0x8000_0000
-        end: 0x2_0000_0000
+        end: 0x200_0000_0000
         desc: "external"
     mgr_port_protocol:
       - "narrow_in"
@@ -78,7 +78,7 @@ endpoints:
   - name: "l2_spm"
     array: [8]
     addr_range:
-      base: 0x3000_0000
+      base: 0x7000_0000
       size: 0x0010_0000
     sbr_port_protocol:
       - "narrow_out"

cfg/snitch_cluster.json

@@ -25,7 +25,7 @@
         wide_trans: 32,
         cluster_base_expose: true,
         alias_region_enable: true,
-        alias_region_base: 0x28000000,
+        alias_region_base: 0x30000000,
         // TODO(fischeti): Check if we need Snitch VM support
         vm_support: false,
         // Timing parameters
@@ -73,7 +73,7 @@
     external_addr_regions: [
         {
             name: "l2spm",
-            address: 0x30000000,
+            address: 0x70000000,
             length: 0x10000000,
             cacheable: true
         },

hw/picobello_pkg.sv

@@ -122,12 +122,12 @@ package picobello_pkg;
     ret.AxiExtRegionStart[0] = 'h2000_0000;
     ret.AxiExtRegionEnd[0]   = 'h8000_0000;
     ret.RegExtRegionIdx[0]   = CshRegExtDramSerialLink;
-    ret.RegExtRegionStart[0] = 'h3100_0000;
-    ret.RegExtRegionEnd[0]   = 'h3100_1000;
+    ret.RegExtRegionStart[0] = 'h1800_0000;
+    ret.RegExtRegionEnd[0]   = 'h1800_1000;
     // TODO(fischeti): Currently, I don't see a reason to have a CIE region
-    // Which is why we just put the CIE region after the on-chip region for now
-    ret.Cva6ExtCieOnTop      = 1;
-    ret.Cva6ExtCieLength     = 'h2000_0000;
+    // Which is why we just set the CIE region to size 0 for now
+    ret.Cva6ExtCieOnTop      = 0;
+    ret.Cva6ExtCieLength     = 'h0;
     ret.AddrWidth            = aw_bt'(AxiCfgN.AddrWidth);
     ret.AxiDataWidth         = dw_bt'(AxiCfgN.DataWidth);
     ret.AxiUserWidth         = dw_bt'(max(AxiCfgN.UserWidth, AxiCfgW.UserWidth));
@@ -138,9 +138,10 @@ package picobello_pkg;
     ret.Vga                  = 1'b0;
     // We do not need/want USB
     ret.Usb                  = 1'b0;
-    // TODO(fischeti): Check if we need/want an AXI to DRAM
     ret.LlcOutRegionStart    = 'h8000_0000;
-    ret.LlcOutRegionEnd      = 48'h1_0000_0000;
+    ret.LlcOutRegionEnd      = 'h12_0000_0000;
+    ret.SlinkRegionStart     = 'h100_0000_0000;
+    ret.SlinkRegionEnd       = 'h200_0000_0000;
     return ret;
   endfunction
 

iis-env.sh

@@ -14,5 +14,7 @@ if [ ! -d ".venv" ]; then
   make python-venv
 fi
 
-# Activate the python venv
-source .venv/bin/activate
+# Activate the python venv only if not already active
+if [ -z "$VIRTUAL_ENV" ] || [ "$VIRTUAL_ENV" != "$(realpath .venv)" ]; then
+  source .venv/bin/activate
+fi

sw/cheshire/tests/simple_offload.c

@@ -8,7 +8,7 @@
 #include "picobello_addrmap.h"
 
 // This needs to be in a region which is not cached
-volatile uint32_t (*return_code_array)[CFG_CLUSTER_NR_CORES] = (uint32_t (*)[CFG_CLUSTER_NR_CORES])0x30008000;
+volatile uint32_t (*return_code_array)[CFG_CLUSTER_NR_CORES] = (uint32_t (*)[CFG_CLUSTER_NR_CORES])0x70008000;
 
 int main() {
 

sw/include/picobello_addrmap.h

@@ -38,7 +38,7 @@
 #define PB_SNITCH_CL_CLINT_SET_ADDR(idx) (PB_SNITCH_CL_PERIPH_BASE_ADDR(idx) + SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_REG_OFFSET)
 #define PB_SNITCH_CL_CLINT_CLEAR_ADDR(idx) (PB_SNITCH_CL_PERIPH_BASE_ADDR(idx) + SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_REG_OFFSET)
 
-#define PB_L2_BASE_ADDR 0x30000000
+#define PB_L2_BASE_ADDR 0x70000000
 #define PB_L2_END_ADDR 0x80000000
 
 #endif // _PICOBELLO_MEMORY_MAP

sw/snitch/memory.ld

@@ -4,5 +4,5 @@
 
 MEMORY
 {
-    L3 (rwxa) : ORIGIN = 0x30000000, LENGTH = 0x80000000
+    L3 (rwxa) : ORIGIN = 0x70000000, LENGTH = 0x10000000
 }

target/sim/src/fixture_picobello_top.sv

@@ -24,9 +24,6 @@ module fixture_picobello_top;
   logic [1:0] boot_mode;
   logic       rtc;
 
-  axi_llc_req_t axi_llc_mst_req;
-  axi_llc_rsp_t axi_llc_mst_rsp;
-
   logic jtag_tck;
   logic jtag_trst_n;
   logic jtag_tms;
@@ -128,8 +125,51 @@ module fixture_picobello_top;
   axi_mst_req_t axi_slink_mst_req;
   axi_mst_rsp_t axi_slink_mst_rsp;
 
+  axi_llc_req_t axi_llc_mst_req;
+  axi_llc_rsp_t axi_llc_mst_rsp;
+
   assign axi_slink_mst_req = '0;
 
+  // Mirror instance of serial link, reflecting DRAM on FPGA
+  serial_link #(
+    .axi_req_t  (axi_llc_req_t),
+    .axi_rsp_t  (axi_llc_rsp_t),
+    .cfg_req_t  (reg_req_t),
+    .cfg_rsp_t  (reg_rsp_t),
+    .aw_chan_t  (axi_llc_aw_chan_t),
+    .ar_chan_t  (axi_llc_ar_chan_t),
+    .r_chan_t   (axi_llc_r_chan_t),
+    .w_chan_t   (axi_llc_w_chan_t),
+    .b_chan_t   (axi_llc_b_chan_t),
+    .hw2reg_t   (serial_link_single_channel_reg_pkg::serial_link_single_channel_hw2reg_t),
+    .reg2hw_t   (serial_link_single_channel_reg_pkg::serial_link_single_channel_reg2hw_t),
+    .NumChannels(SlinkNumChan),
+    .NumLanes   (SlinkNumLanes),
+    .MaxClkDiv  (SlinkMaxClkDiv)
+  ) i_dram_serial_link (
+    .clk_i        (clk),
+    .rst_ni       (rst_n),
+    .clk_sl_i     (clk),
+    .rst_sl_ni    (rst_n),
+    .clk_reg_i    (clk),
+    .rst_reg_ni   (rst_n),
+    .testmode_i   (test_mode),
+    .axi_in_req_i ('0),
+    .axi_in_rsp_o (),
+    .axi_out_req_o(axi_llc_mst_req),
+    .axi_out_rsp_i(axi_llc_mst_rsp),
+    .cfg_req_i    ('0),
+    .cfg_rsp_o    (),
+    .ddr_rcv_clk_i(dram_slink_rcv_clk_o),
+    .ddr_rcv_clk_o(dram_slink_rcv_clk_i),
+    .ddr_i        (dram_slink_o),
+    .ddr_o        (dram_slink_i),
+    .isolated_i   ('0),
+    .isolate_o    (),
+    .clk_ena_o    (),
+    .reset_no     ()
+  );
+
   vip_cheshire_soc #(
     .DutCfg           (CheshireCfg),
     .UseDramSys       (1'b0),