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Backend: Formatting
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@TheMightyDuckOfDoom
TheMightyDuckOfDoom committed Aug 28, 2023
1 parent a767646 commit a4699fe
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Showing 17 changed files with 239 additions and 310 deletions.
304 changes: 121 additions & 183 deletions src/backend/src/idma_backend.sv.tpl
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46 changes: 23 additions & 23 deletions src/backend/src/idma_backend_synth.sv.tpl
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Original file line number Diff line number Diff line change
Expand Up @@ -13,29 +13,29 @@ module idma_backend_synth${name_uniqueifier} #(
/// Should both data shifts be done before the dataflow element?
/// If this is enabled, then the data inserted into the dataflow element
/// will no longer be word aligned, but only a single shifter is needed
parameter bit CombinedShifter = 1'b0,
parameter bit CombinedShifter = 1'b0,
/// Data width
parameter int unsigned DataWidth = 32'd32,
parameter int unsigned DataWidth = 32'd32,
/// Address width
parameter int unsigned AddrWidth = 32'd32,
parameter int unsigned AddrWidth = 32'd32,
/// AXI user width
parameter int unsigned UserWidth = 32'd1,
parameter int unsigned UserWidth = 32'd1,
/// AXI ID width
parameter int unsigned AxiIdWidth = 32'd1,
parameter int unsigned AxiIdWidth = 32'd1,
/// Number of transaction that can be in-flight concurrently
parameter int unsigned NumAxInFlight = 32'd3,
parameter int unsigned NumAxInFlight = 32'd3,
/// The depth of the internal reorder buffer:
/// - '2': minimal possible configuration
/// - '3': efficiently handle misaligned transfers (recommended)
parameter int unsigned BufferDepth = 32'd3,
parameter int unsigned BufferDepth = 32'd3,
/// With of a transfer: max transfer size is `2**TFLenWidth` bytes
parameter int unsigned TFLenWidth = 32'd32,
parameter int unsigned TFLenWidth = 32'd32,
/// The depth of the memory system the backend is attached to
parameter int unsigned MemSysDepth = 32'd0,
parameter int unsigned MemSysDepth = 32'd0,
/// Mask invalid data on the manager interface
parameter bit MaskInvalidData = 1'b1,
parameter bit MaskInvalidData = 1'b1,
/// Should the `R`-`AW` coupling hardware be present? (recommended)
parameter bit RAWCouplingAvail = \
parameter bit RAWCouplingAvail = \
% if one_read_port and one_write_port and ('axi' in used_read_protocols) and ('axi' in used_write_protocols):
1,
% else:
Expand All @@ -44,35 +44,35 @@ module idma_backend_synth${name_uniqueifier} #(
/// Should hardware legalization be present? (recommended)
/// If not, software legalization is required to ensure the transfers are
/// AXI4-conformal
parameter bit HardwareLegalizer = 1'b1,
parameter bit HardwareLegalizer = 1'b1,
/// Reject zero-length transfers
parameter bit RejectZeroTransfers = 1'b1,
parameter bit RejectZeroTransfers = 1'b1,
/// Should the error handler be present?
parameter bit ErrorHandling = 1'b\
parameter bit ErrorHandling = 1'b\
% if one_read_port and one_write_port and ('axi' in used_read_protocols) and ('axi' in used_write_protocols):
1,
% else:
0,
%endif
// Dependent parameters; do not override!
/// Strobe Width (do not override!)
parameter int unsigned StrbWidth = DataWidth / 8,
parameter int unsigned StrbWidth = DataWidth / 8,
/// Offset Width (do not override!)
parameter int unsigned OffsetWidth = $clog2(StrbWidth),
parameter int unsigned OffsetWidth = $clog2(StrbWidth),
/// Address type (do not override!)
parameter type addr_t = logic[AddrWidth-1:0],
parameter type addr_t = logic[AddrWidth-1:0],
/// Data type (do not override!)
parameter type data_t = logic[DataWidth-1:0],
parameter type data_t = logic[DataWidth-1:0],
/// Strobe type (do not override!)
parameter type strb_t = logic[StrbWidth-1:0],
parameter type strb_t = logic[StrbWidth-1:0],
/// User type (do not override!)
parameter type user_t = logic[UserWidth-1:0],
parameter type user_t = logic[UserWidth-1:0],
/// ID type (do not override!)
parameter type id_t = logic[AxiIdWidth-1:0],
parameter type id_t = logic[AxiIdWidth-1:0],
/// Transfer length type (do not override!)
parameter type tf_len_t = logic[TFLenWidth-1:0],
parameter type tf_len_t = logic[TFLenWidth-1:0],
/// Offset type (do not override!)
parameter type offset_t = logic[OffsetWidth-1:0]
parameter type offset_t = logic[OffsetWidth-1:0]
)(
input logic clk_i,
input logic rst_ni,
Expand Down
4 changes: 2 additions & 2 deletions src/backend/src/idma_channel_coupler.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -120,7 +120,7 @@ module idma_channel_coupler #(
assign aw_req_in.decoupled = aw_decouple_aw_i;

// aw payload is just connected to fifo
assign aw_req_o = aw_req_out.aw;
assign aw_req_o = aw_req_out.aw;

// use a credit counter to keep track of AWs to send
always_comb begin : proc_credit_cnt
Expand All @@ -129,7 +129,7 @@ module idma_channel_coupler #(
aw_to_send_d = aw_to_send_q;

// if we bypass the logic
aw_sent = aw_req_out.decoupled & aw_valid;
aw_sent = aw_req_out.decoupled & aw_valid;

// first is asserted and aw is ready -> just send AW out
// without changing the credit counter value
Expand Down
15 changes: 7 additions & 8 deletions src/backend/src/idma_dataflow_element.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -41,15 +41,14 @@ module idma_dataflow_element #(
.clk_i,
.rst_ni,
.testmode_i,
.flush_i ( 1'b0 ),
.data_i ( data_i [i] ),
.valid_i ( valid_i [i] ),
.ready_o ( ready_o [i] ),
.data_o ( data_o [i] ),
.valid_o ( valid_o [i] ),
.ready_i ( ready_i [i] )
.flush_i ( 1'b0 ),
.data_i ( data_i [i] ),
.valid_i ( valid_i [i] ),
.ready_o ( ready_o [i] ),
.data_o ( data_o [i] ),
.valid_o ( valid_o [i] ),
.ready_i ( ready_i [i] )
);
end : gen_fifo_buffer

endmodule : idma_dataflow_element

44 changes: 22 additions & 22 deletions src/backend/src/idma_error_handler.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -55,13 +55,13 @@ module idma_error_handler #(
input logic req_ready_i,

/// The current read address (burst address) injected into the datapath
input addr_t r_addr_i,
input addr_t r_addr_i,
/// The address is consumed by the datapath
input logic r_consume_i,
input logic r_consume_i,
/// The current write address (burst address) injected into the datapath
input addr_t w_addr_i,
input addr_t w_addr_i,
/// The address is consumed by the datapath
input logic w_consume_i,
input logic w_consume_i,

/// Invalidate the current burst transfer, stops emission of requests
output logic legalizer_flush_o,
Expand Down Expand Up @@ -230,9 +230,9 @@ module idma_error_handler #(

// a proper write response (lowest priority)
if (w_dp_rsp_i.resp == axi_pkg::RESP_OKAY & w_dp_valid_i & w_last_burst_i) begin
rsp_o = '0;
rsp_o.last = w_super_last_i;
rsp_valid_o = 1'b1;
rsp_o = '0;
rsp_o.last = w_super_last_i;
rsp_valid_o = 1'b1;
//rb_out_ready = 1'b1; // pop buffer
end

Expand All @@ -250,9 +250,9 @@ module idma_error_handler #(
r_dp_ready_o = 1'b0;
// go to one of the wait states
if (w_last_burst_i) begin
state_d = WAIT_LAST_W;
state_d = WAIT_LAST_W;
end else begin
state_d = WAIT;
state_d = WAIT;
end
end

Expand All @@ -279,8 +279,8 @@ module idma_error_handler #(
if (eh_valid_i) begin
// continue case (~error reporting)
if (eh_i == idma_pkg::CONTINUE) begin
eh_ready_o = 1'b1;
state_d = IDLE;
eh_ready_o = 1'b1;
state_d = IDLE;
end
// abort
if (eh_i == idma_pkg::ABORT) begin
Expand All @@ -289,13 +289,13 @@ module idma_error_handler #(
// - some transfers might complete properly so no flush allowed!
// in this case just continue
if (num_outst_q > 'd1) begin
eh_ready_o = 1'b1;
state_d = IDLE;
eh_ready_o = 1'b1;
state_d = IDLE;
// we are aborting a long transfer (it is still in the legalizer and
// therefore the only active transfer in the datapath)
end else if (num_outst_q == 'd1) begin
eh_ready_o = 1'b1;
state_d = LEG_FLUSH;
eh_ready_o = 1'b1;
state_d = LEG_FLUSH;
// the counter is 0 -> no transfer in the datapath. This is an impossible
// state
end else begin
Expand All @@ -312,7 +312,7 @@ module idma_error_handler #(
WAIT_LAST_W : begin
// continue case (~error reporting)
if (eh_i == idma_pkg::CONTINUE) begin
eh_ready_o = 1'b1;
eh_ready_o = 1'b1;
state_d = EMIT_EXTRA_RSP;
end
// abort
Expand All @@ -322,13 +322,13 @@ module idma_error_handler #(
// - some transfers might complete properly so no flush allowed!
// in this case just continue
if (num_outst_q > 'd1) begin
eh_ready_o = 1'b1;
state_d = EMIT_EXTRA_RSP;
eh_ready_o = 1'b1;
state_d = EMIT_EXTRA_RSP;
// we are aborting a long transfer (it is still in the legalizer and
// therefore the only active transfer in the datapath)
end else if (num_outst_q == 'd1) begin
eh_ready_o = 1'b1;
state_d = LEG_FLUSH;
eh_ready_o = 1'b1;
state_d = LEG_FLUSH;
// the counter is 0 -> no transfer in the datapath. This is an impossible
// state
end else begin
Expand Down Expand Up @@ -356,8 +356,8 @@ module idma_error_handler #(
r_dp_ready_o = 1'b1;
// once the datapath is idle return to idle
if (!dp_busy_i) begin
state_d = EMIT_EXTRA_RSP;
legalizer_kill_o = 1'b1;
state_d = EMIT_EXTRA_RSP;
legalizer_kill_o = 1'b1;
end
end

Expand Down
16 changes: 8 additions & 8 deletions src/backend/src/idma_legalizer.sv.tpl
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Original file line number Diff line number Diff line change
Expand Up @@ -143,9 +143,9 @@ ${database[p]['max_beats_per_burst']} * StrbWidth > ${database[p]['page_size']}\
logic w_tf_ena;

// page boundaries
page_len_t r_num_bytes_to_pb;
page_len_t w_num_bytes_to_pb;
page_len_t c_num_bytes_to_pb;
page_len_t r_num_bytes_to_pb;
page_len_t w_num_bytes_to_pb;
page_len_t c_num_bytes_to_pb;

// read process
page_len_t r_num_bytes_possible;
Expand Down Expand Up @@ -524,9 +524,9 @@ w_tf_q.length[PageAddrWidth:0] ),
//--------------------------------------
if (kill_i) begin
// kill the current state
r_tf_d = '0;
r_tf_d = '0;
w_tf_d = '0;
r_done = 1'b1;
w_tf_d = '0;
w_done = 1'b1;
end

Expand Down Expand Up @@ -790,9 +790,9 @@ ${database[protocol]['legalizer_write_data_path']}
//--------------------------------------
// State
//--------------------------------------
`FF(opt_tf_q, opt_tf_d, '0, clk_i, rst_ni)
`FFL(r_tf_q, r_tf_d, r_tf_ena, '0, clk_i, rst_ni)
`FFL(w_tf_q, w_tf_d, w_tf_ena, '0, clk_i, rst_ni)
`FF (opt_tf_q, opt_tf_d, '0, clk_i, rst_ni)
`FFL(r_tf_q, r_tf_d, r_tf_ena, '0, clk_i, rst_ni)
`FFL(w_tf_q, w_tf_d, w_tf_ena, '0, clk_i, rst_ni)
//--------------------------------------
Expand Down
12 changes: 6 additions & 6 deletions src/backend/src/protocol_managers/axi/idma_axi_read.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -55,9 +55,9 @@ module idma_axi_read #(
output logic ar_ready_o,

/// AXI4+ATOP read manager port request
output read_req_t read_req_o,
output read_req_t read_req_o,
/// AXI4+ATOP read manager port response
input read_rsp_t read_rsp_i,
input read_rsp_t read_rsp_i,

/// Response channel valid and ready
output logic r_chan_ready_o,
Expand Down Expand Up @@ -167,7 +167,7 @@ module idma_axi_read #(

// once valid data is applied, it can be pushed in all the selected (mask_in) buffers
// be sure the response channel is ready
assign in_valid = read_rsp_i.r_valid & in_ready & r_dp_ready_i;
assign in_valid = read_rsp_i.r_valid & in_ready & r_dp_ready_i;
assign buffer_in_valid_o = in_valid ? mask_in : '0;

// r_dp_ready_o is triggered by the last element arriving from the read
Expand All @@ -190,11 +190,11 @@ module idma_axi_read #(
// Unused AXI signals
//--------------------------------------
assign read_req_o.aw_valid = 1'b0;
assign read_req_o.w_valid = 1'b0;
assign read_req_o.b_ready = 1'b0;
assign read_req_o.w_valid = 1'b0;
assign read_req_o.b_ready = 1'b0;

assign read_req_o.aw = '0;
assign read_req_o.w = '0;
assign read_req_o.w = '0;

//--------------------------------------
// State
Expand Down
21 changes: 10 additions & 11 deletions src/backend/src/protocol_managers/axi/idma_axi_write.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -180,8 +180,8 @@ module idma_axi_write #(
// always_comb process implements masking of invalid data
always_comb begin : proc_mask
// defaults
write_req_o.w.data = '0;
write_req_o.w.strb = '0;
write_req_o.w.data = '0;
write_req_o.w.strb = '0;
buffer_data_masked = '0;
// control the write to the bus apply data to the bus only if data should be written
if (ready_to_write == 1'b1 & !dp_poison_i) begin
Expand All @@ -200,8 +200,8 @@ module idma_axi_write #(
// not used signal
assign buffer_data_masked = '0;
// simpler: direct connection
assign write_req_o.w.data = buffer_out_i;
assign write_req_o.w.strb = dp_poison_i ? '0 : mask_out;
assign write_req_o.w.data = buffer_out_i;
assign write_req_o.w.strb = dp_poison_i ? '0 : mask_out;
end

// the w last signal should only be applied to the bus if an actual transfer happens
Expand All @@ -214,11 +214,11 @@ module idma_axi_write #(
always_comb begin : proc_write_control
// defaults:
// beat counter
w_num_beats_d = w_num_beats_q;
w_cnt_valid_d = w_cnt_valid_q;
w_num_beats_d = w_num_beats_q;
w_cnt_valid_d = w_cnt_valid_q;
// mask control
first_w = 1'b0;
last_w = 1'b0;
first_w = 1'b0;
last_w = 1'b0;

// differentiate between the burst and non-burst case. If a transfer
// consists just of one beat the counters are disabled
Expand Down Expand Up @@ -279,10 +279,9 @@ module idma_axi_write #(
//--------------------------------------
// Unused AXI signals
//--------------------------------------
assign write_req_o.ar = '0;
assign write_req_o.ar_valid = 1'b0;
assign write_req_o.r_ready = 1'b0;

assign write_req_o.ar = '0;
assign write_req_o.r_ready = 1'b0;

//--------------------------------------
// State
Expand Down
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