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CVA6: Extend CVA6 system wrapper to include 2D support
--------- Co-authored-by: Alessandro Ottaviano <aottaviano@iis.ee.ethz.ch>
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,57 @@ | ||
| // Generated register defines for idma_reg64_2d_frontend | ||
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| // Copyright information found in source file: | ||
| // Copyright 2022 ETH Zurich and University of Bologna. | ||
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| // Licensing information found in source file: | ||
| // Licensed under Solderpad Hardware License, Version 0.51 | ||
| // SPDX-License-Identifier: SHL-0.51 | ||
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| #ifndef _IDMA_REG64_2D_FRONTEND_REG_DEFS_ | ||
| #define _IDMA_REG64_2D_FRONTEND_REG_DEFS_ | ||
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| #ifdef __cplusplus | ||
| extern "C" { | ||
| #endif | ||
| // Register width | ||
| #define IDMA_REG64_2D_FRONTEND_PARAM_REG_WIDTH 64 | ||
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| // Source Address | ||
| #define IDMA_REG64_2D_FRONTEND_SRC_ADDR_REG_OFFSET 0x0 | ||
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| // Destination Address | ||
| #define IDMA_REG64_2D_FRONTEND_DST_ADDR_REG_OFFSET 0x8 | ||
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| // Number of bytes | ||
| #define IDMA_REG64_2D_FRONTEND_NUM_BYTES_REG_OFFSET 0x10 | ||
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| // Configuration Register for DMA settings | ||
| #define IDMA_REG64_2D_FRONTEND_CONF_REG_OFFSET 0x18 | ||
| #define IDMA_REG64_2D_FRONTEND_CONF_DECOUPLE_BIT 0 | ||
| #define IDMA_REG64_2D_FRONTEND_CONF_DEBURST_BIT 1 | ||
| #define IDMA_REG64_2D_FRONTEND_CONF_SERIALIZE_BIT 2 | ||
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| // DMA Status | ||
| #define IDMA_REG64_2D_FRONTEND_STATUS_REG_OFFSET 0x20 | ||
| #define IDMA_REG64_2D_FRONTEND_STATUS_BUSY_BIT 0 | ||
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| // Next ID, launches transfer, returns 0 if transfer not set up properly. | ||
| #define IDMA_REG64_2D_FRONTEND_NEXT_ID_REG_OFFSET 0x28 | ||
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| // Get ID of finished transactions. | ||
| #define IDMA_REG64_2D_FRONTEND_DONE_REG_OFFSET 0x30 | ||
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| // Source Stride | ||
| #define IDMA_REG64_2D_FRONTEND_STRIDE_SRC_REG_OFFSET 0x38 | ||
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| // Destination Stride | ||
| #define IDMA_REG64_2D_FRONTEND_STRIDE_DST_REG_OFFSET 0x40 | ||
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| // Number of 2D repetitions | ||
| #define IDMA_REG64_2D_FRONTEND_NUM_REPETITIONS_REG_OFFSET 0x48 | ||
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| #ifdef __cplusplus | ||
| } // extern "C" | ||
| #endif | ||
| #endif // _IDMA_REG64_2D_FRONTEND_REG_DEFS_ | ||
| // End generated register defines for idma_reg64_2d_frontend |
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src/frontends/register_64bit_2d/idma_reg64_2d_frontend.hjson
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,142 @@ | ||
| // Copyright 2022 ETH Zurich and University of Bologna. | ||
| // Solderpad Hardware License, Version 0.51, see LICENSE for details. | ||
| // SPDX-License-Identifier: SHL-0.51 | ||
| // Licensed under Solderpad Hardware License, Version 0.51 | ||
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| { | ||
| name: "idma_reg64_2d_frontend", | ||
| clock_primary: "clk_i", | ||
| reset_primary: "rst_ni", | ||
| bus_interfaces: [ | ||
| { protocol: "reg_iface", | ||
| direction: "device" | ||
| } | ||
| ], | ||
| regwidth: "64", | ||
| registers: [ | ||
| { name: "src_addr", | ||
| desc: "Source Address", | ||
| swaccess: "rw", | ||
| hwaccess: "hro", | ||
| fields: [ | ||
| { bits: "63:0", | ||
| name: "src_addr", | ||
| desc: "Source Address" | ||
| } | ||
| ] | ||
| }, | ||
| { name: "dst_addr", | ||
| desc: "Destination Address", | ||
| swaccess: "rw", | ||
| hwaccess: "hro", | ||
| fields: [ | ||
| { bits: "63:0", | ||
| name: "dst_addr", | ||
| desc: "Destination Address" | ||
| } | ||
| ] | ||
| }, | ||
| { name: "num_bytes", | ||
| desc: "Number of bytes", | ||
| swaccess: "rw", | ||
| hwaccess: "hro", | ||
| fields: [ | ||
| { bits: "63:0", | ||
| name: "num_bytes", | ||
| desc: "Number of bytes" | ||
| } | ||
| ] | ||
| }, | ||
| { name: "conf", | ||
| desc: "Configuration Register for DMA settings", | ||
| swaccess: "rw", | ||
| hwaccess: "hro", | ||
| fields: [ | ||
| { bits: "0", | ||
| name: "decouple", | ||
| desc: "Decouple enable" | ||
| }, | ||
| { bits: "1", | ||
| name: "deburst", | ||
| desc: "Deburst enable" | ||
| }, | ||
| { bits: "2", | ||
| name: "serialize", | ||
| desc: "Serialize enable" | ||
| } | ||
| ] | ||
| }, | ||
| { name: "status", | ||
| desc: "DMA Status", | ||
| swaccess: "ro", | ||
| hwaccess: "hwo", | ||
| hwext: "true", | ||
| fields: [ | ||
| { bits: "0", | ||
| name: "busy", | ||
| desc: "DMA busy" | ||
| } | ||
| ] | ||
| }, | ||
| { name: "next_id", | ||
| desc: "Next ID, launches transfer, returns 0 if transfer not set up properly.", | ||
| swaccess: "ro", | ||
| hwaccess: "hrw", | ||
| hwext: "true", | ||
| hwre: "true", | ||
| fields: [ | ||
| { bits: "63:0", | ||
| name: "next_id", | ||
| desc: "Next ID, launches transfer, returns 0 if transfer not set up properly." | ||
| } | ||
| ] | ||
| }, | ||
| { name: "done", | ||
| desc: "Get ID of finished transactions.", | ||
| swaccess: "ro", | ||
| hwaccess: "hrw", | ||
| hwext: "true", | ||
| hwre: "true", | ||
| fields: [ | ||
| { bits: "63:0", | ||
| name: "done", | ||
| desc: "Get ID of finished transactions." | ||
| } | ||
| ] | ||
| }, | ||
| { name: "stride_src", | ||
| desc: "Source Stride", | ||
| swaccess: "rw", | ||
| hwaccess: "hro", | ||
| fields: [ | ||
| { bits: "63:0", | ||
| name: "stride_src", | ||
| desc: "Source Stride" | ||
| } | ||
| ] | ||
| }, | ||
| { name: "stride_dst" | ||
| desc: "Destination Stride", | ||
| swaccess: "rw", | ||
| hwaccess: "hro", | ||
| fields: [ | ||
| { bits: "63:0", | ||
| name: "stride_dst", | ||
| desc: "Destination Stride" | ||
| } | ||
| ] | ||
| }, | ||
| { name: "num_repetitions" | ||
| desc: "Number of 2D repetitions", | ||
| swaccess: "rw", | ||
| hwaccess: "hro", | ||
| fields: [ | ||
| { bits: "63:0", | ||
| name: "num_repetitions", | ||
| desc: "Number of 2D repetitions", | ||
| resval: "0" | ||
| } | ||
| ] | ||
| } | ||
| ] | ||
| } |
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