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Made strobe width of HWPE Stream Fifo a parameter #18

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Made strobe width of HWPE Stream Fifo a parameter #18

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0a54570
Added configurable strobe with to stream fifo.
May 31, 2024
6d9888d
Added strobe parameter to all modules and updated comments.
Jun 10, 2024
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21 changes: 12 additions & 9 deletions rtl/basic/hwpe_stream_fence.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -29,20 +29,23 @@
* .. _hwpe_stream_fence_params:
* .. table:: **hwpe_stream_fence** design-time parameters.
*
* +------------------+-------------+---------------------------------------------+
* | **Name** | **Default** | **Description** |
* +------------------+-------------+---------------------------------------------+
* | *NB_STREAMS* | 2 | Number of input/output HWPE-Stream streams. |
* +------------------+-------------+---------------------------------------------+
* | *DATA_WIDTH* | 32 | Width of the HWPE-Stream streams. |
* +------------------+-------------+---------------------------------------------+
* +------------------+----------------+---------------------------------------------+
* | **Name** | **Default** | **Description** |
* +------------------+----------------+---------------------------------------------+
* | *NB_STREAMS* | 2 | Number of input/output HWPE-Stream streams. |
* +------------------+----------------+---------------------------------------------+
* | *DATA_WIDTH* | 32 | Width of the HWPE-Stream streams. |
* +------------------+----------------+---------------------------------------------+
* | *STRB_WIDTH* | DATA_WIDTH / 8 | Width of the HWPE-Stream strobe signal. |
* +------------------+----------------+---------------------------------------------+
*/

import hwpe_stream_package::*;

module hwpe_stream_fence #(
parameter int unsigned NB_STREAMS = 2,
parameter int unsigned DATA_WIDTH = 32
parameter int unsigned DATA_WIDTH = 32,
parameter int unsigned STRB_WIDTH = DATA_WIDTH/8
)
(
input logic clk_i,
Expand All @@ -59,7 +62,7 @@ module hwpe_stream_fence #(
logic out_valid;
logic [NB_STREAMS-1:0] fence_state_q, fence_state_d;
logic [NB_STREAMS-1:0][DATA_WIDTH-1:0] data_q;
logic [NB_STREAMS-1:0][DATA_WIDTH/8-1:0] strb_q;
logic [NB_STREAMS-1:0][STRB_WIDTH-1:0] strb_q;

generate
for(genvar ii=0; ii<NB_STREAMS; ii++) begin : binding
Expand Down
21 changes: 11 additions & 10 deletions rtl/basic/hwpe_stream_merge.sv
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Expand Up @@ -35,20 +35,23 @@
* .. _hwpe_stream_merge_params:
* .. table:: **hwpe_stream_merge** design-time parameters.
*
* +------------------+-------------+---------------------------------------------+
* | **Name** | **Default** | **Description** |
* +------------------+-------------+---------------------------------------------+
* | *NB_IN_STREAMS* | 2 | Number of input HWPE-Stream streams. |
* +------------------+-------------+---------------------------------------------+
* | *DATA_WIDTH_IN* | 32 | Width of the input HWPE-Stream streams. |
* +------------------+-------------+---------------------------------------------+
* +------------------+------------------+-----------------------------------------------+
* | **Name** | **Default** | **Description** |
* +------------------+------------------+-----------------------------------------------+
* | *NB_IN_STREAMS* | 2 | Number of input HWPE-Stream streams. |
* +------------------+------------------+-----------------------------------------------+
* | *DATA_WIDTH_IN* | 32 | Width of the input HWPE-Stream streams. |
* +------------------+------------------+-----------------------------------------------+
* | *STRB_WIDTH_IN* |DATA_WIDTH_IN / 8 | Width of the input HWPE-Stream strobe signal. |
* +------------------+------------------+-----------------------------------------------+
*/

import hwpe_stream_package::*;

module hwpe_stream_merge #(
parameter int unsigned NB_IN_STREAMS = 2,
parameter int unsigned DATA_WIDTH_IN = 32
parameter int unsigned DATA_WIDTH_IN = 32,
parameter int unsigned STRB_WIDTH_IN = DATA_WIDTH_IN/8
)
(
input logic clk_i,
Expand All @@ -59,8 +62,6 @@ module hwpe_stream_merge #(
hwpe_stream_intf_stream.source pop_o
);

parameter STRB_WIDTH_IN = DATA_WIDTH_IN / 8;

logic [NB_IN_STREAMS-1:0] stream_valid;

generate
Expand Down
41 changes: 22 additions & 19 deletions rtl/basic/hwpe_stream_serialize.sv
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Expand Up @@ -22,24 +22,26 @@
* .. _hwpe_stream_serialize_params:
* .. table:: **hwpe_stream_serialize** design-time parameters.
*
* +------------------+-------------+-------------------------------------------------------+
* | **Name** | **Default** | **Description** |
* +------------------+-------------+-------------------------------------------------------+
* | *NB_IN_STREAMS* | 2 | Number of input HWPE-Stream streams. |
* +------------------+-------------+-------------------------------------------------------+
* | *DATA_WIDTH* | 32 | Width of the HWPE-Stream streams. |
* +------------------+-------------+-------------------------------------------------------+
* | *CONTIG_LIMIT* | 1024 | Maximum number of contiguous packets per stream. |
* +------------------+-------------+-------------------------------------------------------+
* | *SYNC_READY* | 0 | If 0, each incoming stream is handshaken separately, |
* | | | which means that their producers must be independent. |
* | | | If 1, the ready signal is "fenced", which means that |
* | | | all streams wait for the last stream to be ready to |
* | | | progress. This is useful, for example, when there is |
* | | | a single producer (e.g., `hwpe_stream_split`). Care |
* | | | must be taken to deadlocks, typically by inserting a |
* | | | decoupling FIFO. |
* +------------------+-------------+-------------------------------------------------------+
* +------------------+----------------+-------------------------------------------------------+
* | **Name** | **Default** | **Description** |
* +------------------+----------------+-------------------------------------------------------+
* | *NB_IN_STREAMS* | 2 | Number of input HWPE-Stream streams. |
* +------------------+----------------+-------------------------------------------------------+
* | *DATA_WIDTH* | 32 | Width of the HWPE-Stream streams. |
* +------------------+----------------+-------------------------------------------------------+
* | *STRB_WIDTH* | DATA_WIDTH / 8 | Width of the HWPE-Stream strobe signal. |
* +------------------+----------------+-------------------------------------------------------+
* | *CONTIG_LIMIT* | 1024 | Maximum number of contiguous packets per stream. |
* +------------------+----------------+-------------------------------------------------------+
* | *SYNC_READY* | 0 | If 0, each incoming stream is handshaken separately, |
* | | | which means that their producers must be independent. |
* | | | If 1, the ready signal is "fenced", which means that |
* | | | all streams wait for the last stream to be ready to |
* | | | progress. This is useful, for example, when there is |
* | | | a single producer (e.g., `hwpe_stream_split`). Care |
* | | | must be taken to deadlocks, typically by inserting a |
* | | | decoupling FIFO. |
* +------------------+----------------+-------------------------------------------------------+
*
* .. tabularcolumns:: |l|l|J|
* .. _hwpe_stream_serialize_ctrl:
Expand All @@ -61,6 +63,7 @@ module hwpe_stream_serialize #(
parameter int unsigned NB_IN_STREAMS = 2,
parameter int unsigned CONTIG_LIMIT = 1024,
parameter int unsigned DATA_WIDTH = 32,
parameter int unsigned STRB_WIDTH = DATA_WIDTH/8,
parameter logic SYNC_READY = 1'b0
)
(
Expand All @@ -80,7 +83,7 @@ module hwpe_stream_serialize #(
// boilerplate for SystemVerilog compliance
logic [NB_IN_STREAMS-1:0][DATA_WIDTH-1:0] push_data;
logic [NB_IN_STREAMS-1:0] push_valid;
logic [NB_IN_STREAMS-1:0][DATA_WIDTH/8-1:0] push_strb;
logic [NB_IN_STREAMS-1:0][STRB_WIDTH-1:0] push_strb;
logic [NB_IN_STREAMS-1:0] push_ready;

generate
Expand Down
21 changes: 12 additions & 9 deletions rtl/basic/hwpe_stream_split.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -35,20 +35,23 @@
* .. _hwpe_stream_split_params:
* .. table:: **hwpe_stream_split** design-time parameters.
*
* +------------------+-------------+---------------------------------------------+
* | **Name** | **Default** | **Description** |
* +------------------+-------------+---------------------------------------------+
* | *NB_OUT_STREAMS* | 2 | Number of output HWPE-Stream streams. |
* +------------------+-------------+---------------------------------------------+
* | *DATA_WIDTH_IN* | 128 | Width of the input HWPE-Stream stream. |
* +------------------+-------------+---------------------------------------------+
* +------------------+-------------------+------------------------------------------------+
* | **Name** | **Default** | **Description** |
* +------------------+-------------------+------------------------------------------------+
* | *NB_OUT_STREAMS* | 2 | Number of output HWPE-Stream streams. |
* +------------------+-------------------+------------------------------------------------+
* | *DATA_WIDTH_IN* | 128 | Width of the input HWPE-Stream stream. |
* +------------------+-------------------+------------------------------------------------+
* | *STRB_WIDTH_IN* | DATA_WIDTH_IN / 8 | Width of the input HWPE-Stream strobe signal. |
* +------------------+-------------------+------------------------------------------------+
*/

import hwpe_stream_package::*;

module hwpe_stream_split #(
parameter int unsigned NB_OUT_STREAMS = 2,
parameter int unsigned DATA_WIDTH_IN = 128
parameter int unsigned DATA_WIDTH_IN = 128,
parameter int unsigned STRB_WIDTH_IN = DATA_WIDTH_IN/8
)
(
input logic clk_i,
Expand All @@ -60,7 +63,7 @@ module hwpe_stream_split #(
);

parameter int unsigned DATA_WIDTH_OUT = DATA_WIDTH_IN/NB_OUT_STREAMS;
parameter int unsigned STRB_WIDTH_OUT = DATA_WIDTH_OUT/8;
parameter int unsigned STRB_WIDTH_OUT = STRB_WIDTH_IN/NB_OUT_STREAMS;

logic [NB_OUT_STREAMS-1:0] stream_ready;

Expand Down
39 changes: 21 additions & 18 deletions rtl/fifo/hwpe_stream_fifo.sv
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Expand Up @@ -33,17 +33,19 @@
* .. _hwpe_stream_fifo_params:
* .. table:: **hwpe_stream_fifo** design-time parameters.
*
* +------------------------+--------------+--------------------------------------------------------------------------------------+
* | **Name** | **Default** | **Description** |
* +------------------------+--------------+--------------------------------------------------------------------------------------+
* | *DATA_WIDTH* | 32 | Width of the HWPE-Streams (typically multiple of 32, but this module does not care). |
* +------------------------+--------------+--------------------------------------------------------------------------------------+
* | *FIFO_DEPTH* | 8 | Depth of the FIFO queue (multiple of 2). |
* +------------------------+--------------+--------------------------------------------------------------------------------------+
* | *LATCH_FIFO* | 0 | If 1, use latches instead of flip-flops (requires special constraints in synthesis). |
* +------------------------+--------------+--------------------------------------------------------------------------------------+
* | *LATCH_FIFO_TEST_WRAP* | 0 | If 1 and *LATCH_FIFO* is 1, wrap latches with BIST wrappers. |
* +------------------------+--------------+--------------------------------------------------------------------------------------+
* +------------------------+----------------+--------------------------------------------------------------------------------------+
* | **Name** | **Default** | **Description** |
* +------------------------+----------------+--------------------------------------------------------------------------------------+
* | *DATA_WIDTH* | 32 | Width of the HWPE-Streams (typically multiple of 32, but this module does not care). |
* +------------------------+----------------+--------------------------------------------------------------------------------------+
* | *STRB_WIDTH* | DATA_WIDTH / 8 | Width of the HWPE-Stream strobe signal. |
* +------------------------+----------------+--------------------------------------------------------------------------------------+
* | *FIFO_DEPTH* | 8 | Depth of the FIFO queue (multiple of 2). |
* +------------------------+----------------+--------------------------------------------------------------------------------------+
* | *LATCH_FIFO* | 0 | If 1, use latches instead of flip-flops (requires special constraints in synthesis). |
* +------------------------+----------------+--------------------------------------------------------------------------------------+
* | *LATCH_FIFO_TEST_WRAP* | 0 | If 1 and *LATCH_FIFO* is 1, wrap latches with BIST wrappers. |
* +------------------------+----------------+--------------------------------------------------------------------------------------+
*
* .. tabularcolumns:: |l|l|J|
* .. _hwpe_stream_fifo_flags:
Expand All @@ -67,6 +69,7 @@ import hwpe_stream_package::*;

module hwpe_stream_fifo #(
parameter int unsigned DATA_WIDTH = 32,
parameter int unsigned STRB_WIDTH = DATA_WIDTH/8,
parameter int unsigned FIFO_DEPTH = 8,
parameter int unsigned LATCH_FIFO = 0,
parameter int unsigned LATCH_FIFO_TEST_WRAP = 0
Expand All @@ -90,7 +93,7 @@ module hwpe_stream_fifo #(

logic [ADDR_DEPTH-1:0] pop_pointer_q, pop_pointer_d;
logic [ADDR_DEPTH-1:0] push_pointer_q, push_pointer_d;
logic [DATA_WIDTH+DATA_WIDTH/8-1:0] fifo_registers[FIFO_DEPTH-1:0];
logic [DATA_WIDTH+STRB_WIDTH-1:0] fifo_registers[FIFO_DEPTH-1:0];
integer i;

assign flags_o.empty = (cs == EMPTY) ? 1'b1 : 1'b0;
Expand Down Expand Up @@ -229,8 +232,8 @@ module hwpe_stream_fifo #(
endcase
end

logic [DATA_WIDTH+DATA_WIDTH/8-1:0] data_out_int;
logic [DATA_WIDTH+DATA_WIDTH/8-1:0] data_in_int;
logic [DATA_WIDTH+STRB_WIDTH-1:0] data_out_int;
logic [DATA_WIDTH+STRB_WIDTH-1:0] data_in_int;

generate
if(LATCH_FIFO == 0) begin : fifo_ff_gen
Expand Down Expand Up @@ -260,7 +263,7 @@ module hwpe_stream_fifo #(

hwpe_stream_fifo_scm #(
.ADDR_WIDTH ( ADDR_DEPTH ),
.DATA_WIDTH ( DATA_WIDTH + DATA_WIDTH/8 )
.DATA_WIDTH ( DATA_WIDTH + STRB_WIDTH )
) i_fifo_latch (
.clk ( clk_i ),
.rst_n ( rst_ni ),
Expand All @@ -279,7 +282,7 @@ module hwpe_stream_fifo #(

hwpe_stream_fifo_scm_test_wrap #(
.ADDR_WIDTH ( ADDR_DEPTH ),
.DATA_WIDTH ( DATA_WIDTH + DATA_WIDTH/8 )
.DATA_WIDTH ( DATA_WIDTH + STRB_WIDTH )
) i_fifo_latch (
.clk ( clk_i ),
.rst_n ( rst_ni ),
Expand All @@ -300,7 +303,7 @@ module hwpe_stream_fifo #(
end
endgenerate

assign pop_o.data = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH+DATA_WIDTH/8-1:DATA_WIDTH/8] : '0;
assign pop_o.strb = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH/8-1:0] : '0;
assign pop_o.data = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH+STRB_WIDTH-1:STRB_WIDTH] : '0;
assign pop_o.strb = (pop_o.valid == 1'b1) ? data_out_int[STRB_WIDTH-1:0] : '0;

endmodule // hwpe_stream_fifo
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