Squash of Luca Codeluppi's thesis - Verif part

.gitignore

@@ -0,0 +1 @@
+config/__pycache__

Bender.lock

@@ -0,0 +1,42 @@
+packages:
+  cluster_interconnect:
+    revision: 1284def6c0b7f7e9355eb093d00883ad9dead1b7
+    version: null
+    source:
+      Git: https://github.com/pulp-platform/cluster_interconnect.git
+    dependencies:
+    - common_cells
+  common_cells:
+    revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb
+    version: 1.37.0
+    source:
+      Git: https://github.com/pulp-platform/common_cells.git
+    dependencies:
+    - common_verification
+    - tech_cells_generic
+  common_verification:
+    revision: fa2630f61666f61d9d78451c4d8b4d1ea403944e
+    version: 0.2.4
+    source:
+      Git: https://github.com/pulp-platform/common_verification.git
+    dependencies: []
+  hwpe-stream:
+    revision: 65c99a4a2f37a79acee800ab0151f67dfb1edef1
+    version: 1.8.0
+    source:
+      Git: https://github.com/pulp-platform/hwpe-stream.git
+    dependencies:
+    - tech_cells_generic
+  l2_tcdm_hybrid_interco:
+    revision: fa55e72859dcfb117a2788a77352193bef94ff2b
+    version: 1.0.0
+    source:
+      Git: https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git
+    dependencies: []
+  tech_cells_generic:
+    revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
+    version: 0.2.13
+    source:
+      Git: https://github.com/pulp-platform/tech_cells_generic.git
+    dependencies:
+    - common_verification

Bender.yml

@@ -62,3 +62,40 @@ sources:
       - rtl/ecc/hci_ecc_interconnect.sv
       - rtl/ecc/hci_ecc_sink.sv
       - rtl/hci_interconnect.sv
+      - target: any(test, test_wrap, test_wrap_netlist)
+        files:
+          # Level 0
+          - verif/sv/common/verification_hci_package.sv
+          # Level 1
+          - verif/sv/clock_and_reset/rst_gen_prova.sv
+          - verif/sv/clock_and_reset/clk_rst_gen_prova.sv
+          - verif/sv/other_modules/application_driver.sv
+          - verif/sv/other_modules/queues_stimuli.sv
+          - verif/sv/other_modules/queues_rdata.sv
+          - verif/sv/other_modules/queues_out.sv
+          - verif/sv/other_modules/arbiter_checker.sv
+          - verif/sv/other_modules/compute_latency_per_transaction.sv
+          - verif/sv/other_modules/compute_througput_and_simtime.sv
+          - verif/sv/other_modules/tcdm_banks_wrap.sv
+          - verif/sv/other_modules/end_simulation_and_final_report.sv
+          - verif/sv/other_modules/progress_bar.sv
+          - verif/sv/other_modules/assign_drivers_to_hwpebranch.sv
+          - verif/sv/other_modules/assign_drivers_to_logbranch.sv
+      - target: test
+        files:
+          # Level 2
+          - verif/sv/tb_top.sv
+      - target: test_wrap
+        files:
+          - rtl/hci_interconnect_wrap.sv
+          # Level 2
+          - backend/sourcecode/tb_top_wrap.sv
+      - target: test_wrap_netlist
+        files:
+          - backend/synopsys/out/hci_interconnect_wrap.v
+          # Level 2
+          - backend/sourcecode/tb_top_wrap_netlist.sv
+      - target: synthesis
+        files:
+          # Level 0
+          - rtl/hci_interconnect_wrap.sv

Makefile

@@ -0,0 +1,140 @@
+include config/config.mk
+
+ROOT_DIR := $(strip $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) # set the absolute path of the directory where the makefile is located
+VLIB ?= vlib
+library ?= work
+VSIM ?= vsim
+top_level ?= hci_tb
+TARGET_BENDER ?= test
+VOPT ?= vopt
+PYTHON ?= python
+PYTHON_STIMULI_SCRIPT ?= verif/stimuli_generator/stimuli_gen_main.py
+N_LOG := $(strip $(shell echo $(N_CORE) + $(N_DMA) + $(N_EXT) | bc))
+
+VLOG_ARGS += -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale \"1 ns / 1 ps\" \"+incdir+$(shell pwd)/include\"
+MACROS_TB := +define+N_HWPE=$(N_HWPE) +define+HWPE_WIDTH=$(HWPE_WIDTH) +define+N_CORE=$(N_CORE) +define+N_DMA=$(N_DMA) +define+N_EXT=$(N_EXT) \
++define+TS_BIT=$(TS_BIT) +define+EXPFIFO=$(EXPFIFO) +define+SEL_LIC=$(SEL_LIC) +define+DATA_WIDTH=$(DATA_WIDTH) +define+TOT_MEM_SIZE=$(TOT_MEM_SIZE) \
++define+N_BANKS=$(N_BANKS) +define+N_TRANSACTION_LOG=$(N_TRANSACTION_LOG) +define+TRANSACTION_RATIO=$(TRANSACTION_RATIO) +define+CLK_PERIOD=$(CLK_PERIOD) \
++define+RST_CLK_CYCLES=$(RST_CLK_CYCLES) +define+MAX_CYCLES_BETWEEN_GNT_RVALID=$(MAX_CYCLES_BETWEEN_GNT_RVALID) +define+RANDOM_GNT=$(RANDOM_GNT) \
++define+PRIORITY_CHECK_MODE_ONE=$(PRIORITY_CHECK_MODE_ONE) +define+PRIORITY_CHECK_MODE_ZERO=$(PRIORITY_CHECK_MODE_ZERO) \
++define+INVERT_PRIO=$(INVERT_PRIO) +define+LOW_PRIO_MAX_STALL=$(LOW_PRIO_MAX_STALL)
+
+define generate_vsim
+	echo 'set ROOT [file normalize [file dirname [info script]]/$3]' > $1
+	bender script vsim --vlog-arg="$(VLOG_ARGS)" $2 --vlog-arg="$(MACROS_TB)" | grep -v "set ROOT" >> $1
+	echo >> $1
+endef
+
+########################
+# 	  DEPENDENCIES     #
+########################
+
+.PHONY: checkout
+## Checkout/update dependencies using Bender
+checkout:
+	bender checkout
+	touch Bender.lock
+	make scripts/compile.tcl
+
+Bender.lock:
+	bender checkout
+	touch Bender.lock
+
+# Create config files for the masters
+clean_setup:
+	rm -rf config/hardware_config/masters_config
+
+setup: clean_setup
+	@for i in $(shell seq 0 $(shell echo $(N_LOG)-1 | bc) ); do \
+		LOG_PATH="config/hardware_config/masters_config/log"$$i"_config.mk"; \
+		echo "Creating log"$$i"_config.mk..."; \
+		mkdir -p config/hardware_config/masters_config; \
+		echo "###########################################" > $$LOG_PATH;  \
+		echo "#	  LOG$$i MEMORY ACCESS PARAMETERS		  #" >> $$LOG_PATH; \
+		echo "###########################################"	>> $$LOG_PATH; \
+		echo -e "\n# Memory access type: 0 (random), 1 (linear), 2 (2D), 3 (3D)" >> $$LOG_PATH; \
+		echo "MEM_ACCESS_TYPE_LOG$$i?=0" >> $$LOG_PATH; \
+		echo "# Starting address in binary (required for linear, 2D, and 3D accesses). Set to 0 if not needed" >> $$LOG_PATH; \
+		echo "START_ADDRESS_LOG$$i?=0" >> $$LOG_PATH; \
+		echo "# Stride0 (required for linear, 2D, and 3D accesses). Set to 0 if not needed" >> $$LOG_PATH; \
+		echo "STRIDE0_LOG$$i?=0" >> $$LOG_PATH; \
+		echo "# Len_d0 (required for 2D and 3D accesses). Set to 0 if not needed" >> $$LOG_PATH; \
+		echo "LEN_D0_LOG$$i?=0" >> $$LOG_PATH; \
+		echo "# Stride1 (required for 2D and 3D accesses). Set to 0 if not needed" >> $$LOG_PATH; \
+		echo "STRIDE1_LOG$$i?=0" >> $$LOG_PATH; \
+		echo "# Len_d1 (required for 3D accesses). Set to 0 if not needed" >> $$LOG_PATH; \
+		echo "LEN_D1_LOG$$i?=0" >> $$LOG_PATH;  \
+		echo "# Stride2 (required for 3D accesses). Set to 0 if not needed" >> $$LOG_PATH;  \
+		echo "STRIDE2_LOG$$i?=0" >> $$LOG_PATH; \
+		echo "Done!";\
+	done
+	@for i in $(shell seq 0 $(shell echo $(N_HWPE)-1 | bc) ); do \
+		HWPE_PATH="config/hardware_config/masters_config/hwpe"$$i"_config.mk"; \
+		echo "Creating hwpe"$$i"_config.mk..."; \
+		mkdir -p config/hardware_config/masters_config; \
+		echo "###########################################" > $$HWPE_PATH;  \
+		echo "#	  HWPE$$i MEMORY ACCESS PARAMETERS	  #" >> $$HWPE_PATH; \
+		echo "###########################################"	>> $$HWPE_PATH; \
+		echo -e "\n# Memory access type: 0 (random), 1 (linear), 2 (2D), 3 (3D)" >> $$HWPE_PATH; \
+		echo "MEM_ACCESS_TYPE_HWPE$$i?=0" >> $$HWPE_PATH; \
+		echo "# Starting address in binary (required for linear, 2D, and 3D accesses). Set to 0 if not needed" >> $$HWPE_PATH; \
+		echo "START_ADDRESS_HWPE$$i?=0" >> $$HWPE_PATH; \
+		echo "# Stride0 (required for linear, 2D, and 3D accesses). Set to 0 if not needed" >> $$HWPE_PATH; \
+		echo "STRIDE0_HWPE$$i?=0" >> $$HWPE_PATH; \
+		echo "# Len_d0 (required for 2D and 3D accesses). Set to 0 if not needed" >> $$HWPE_PATH; \
+		echo "LEN_D0_HWPE$$i?=0" >> $$HWPE_PATH; \
+		echo "# Stride1 (required for 2D and 3D accesses). Set to 0 if not needed" >> $$HWPE_PATH; \
+		echo "STRIDE1_HWPE$$i?=0" >> $$HWPE_PATH; \
+		echo "# Len_d1 (required for 3D accesses). Set to 0 if not needed" >> $$HWPE_PATH; \
+		echo "LEN_D1_HWPE$$i?=0" >> $$HWPE_PATH;  \
+		echo "# Stride2 (required for 3D accesses). Set to 0 if not needed" >> $$HWPE_PATH;  \
+		echo "STRIDE2_HWPE$$i?=0" >> $$HWPE_PATH; \
+		echo "Done!";\
+	done
+
+
+########################
+# 	 CREATE STIMULI    #
+########################
+
+clean_stimuli:
+	@echo -e "\nRemove old stimuli..."
+	@rm -rf verif/simvectors
+
+PYTHON_SIM_AND_HARDWARE_ARGS := --sim_and_hardware_params $(N_BANKS) $(TOT_MEM_SIZE) $(DATA_WIDTH) $(N_CORE) $(N_DMA) $(N_EXT) $(N_HWPE) $(HWPE_WIDTH) $(TRANSACTION_RATIO) $(N_TRANSACTION_LOG) $(CYCLE_OFFSET_LOG) $(CYCLE_OFFSET_HWPE) $(EXACT_OR_MAX_OFFSET)
+PYTHON_LOG_ARGS := $(foreach i, $(shell seq 0 $(shell echo $(N_LOG) - 1 | bc)), --master_log $(MEM_ACCESS_TYPE_LOG$(i)) $(START_ADDRESS_LOG$(i)) $(STRIDE0_LOG$(i)) $(LEN_D0_LOG$(i)) $(STRIDE1_LOG$(i)) $(LEN_D1_LOG$(i)) $(STRIDE2_LOG$(i)))
+PYTHON_HWPE_ARGS := $(foreach i, $(shell seq 0 $(shell echo $(N_HWPE) - 1 | bc)), --master_hwpe $(MEM_ACCESS_TYPE_HWPE$(i)) $(START_ADDRESS_HWPE$(i)) $(STRIDE0_HWPE$(i)) $(LEN_D0_HWPE$(i)) $(STRIDE1_HWPE$(i)) $(LEN_D1_HWPE$(i)) $(STRIDE2_HWPE$(i)))
+
+stimuli: clean_stimuli
+	@echo -e "\n### START! ###"
+	@$(PYTHON) $(PYTHON_STIMULI_SCRIPT) $(PYTHON_SIM_AND_HARDWARE_ARGS) $(PYTHON_LOG_ARGS) $(PYTHON_HWPE_ARGS)
+	@echo -e "\nDONE! New stimuli created"
+
+########################
+#  BUILD AND SIMULATE  #
+########################
+
+clean:
+	rm -rf scripts/compile.tcl
+	rm -rf work
+
+scripts/compile.tcl: | Bender.lock
+	$(call generate_vsim, $@, -t $(TARGET_BENDER) ,..) 
+
+$(library):
+	$(VLIB) $(library)
+
+compile: $(library) scripts/compile.tcl
+	@test -f Bender.lock || { echo "ERROR: Bender.lock file does not exist. Did you run make checkout in bender mode?"; exit 1; }
+	@test -f scripts/compile.tcl || { echo "ERROR: scripts/compile.tcl file does not exist. Did you run make scripts in bender mode?"; exit 1; }
+	$(VSIM) -c -do 'source scripts/compile.tcl; quit' -msgmode both
+
+build: compile
+	$(VOPT) $(compile_flag) -suppress 3053 -suppress 8885 -work $(library)  $(top_level) -o $(top_level)_optimized -debug
+
+run:
+	$(VSIM) +permissive $(questa-flags) $(questa-cmd) -suppress 3053 -suppress 8885 -lib $(library)  +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) +APP=$(elf-bin) +notimingchecks +nospecify  -t 1ps \
+	${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) ++$(cl-bin) | tee sim.log
+
+#include backend/backend.mk
+include backend/backend_copy.mk

README.md

@@ -47,4 +47,34 @@ If you are using HCI IPs for an academic publication, we recommend citing one or
   keywords={Power demand;Design automation;Wearable computers;Pipelines;Gaze tracking;Energy efficiency;Task analysis},
   doi={10.1109/DAC56929.2023.10247945}
 }
+```
+# HCI Verification Environment
+
+This repository also contains an environment for verifying the Heterogeneous Cluster Interconnect (HCI)
+
+## Setup Instructions
+
+Before running the simulation, follow these steps:
+
+1. **Configure HCI Parameters** <br>
+Edit the 'hci_config.mk' file inside config/hardware_config folder and insert the correct configuration values as needed for your verification environment. <br>  
+
+2. **Run Setup**
+```bash
+make setup
+```  
+3. **Configure the Parameters of the Masters** <br>
+Edit the files in the folder /config/hardware_config/masters_config to set the parameters of the masters  
+
+4. **Choose the Test** <br>
+Choose the test in /config/config.mk  
+
+5. **Create stimuli** <br>
+```bash
+make stimuli
+```  
+
+6. **Run the simulation** <br>
+```bash
+make clean build run &
 ```

config/config.mk

@@ -0,0 +1,11 @@
+# Select desired test configuration
+SELECT_TEST ?= bandwidth_check
+
+
+MASTERS_CONFIG_PATH := config/hardware_config/masters_config
+HCI_CONFIG_PATH := config/hardware_config
+SIM_CONFIG_PATH := config/sim_config
+SELECT_TEST_MK := $(SELECT_TEST).mk
+-include $(MASTERS_CONFIG_PATH)/*.mk
+include $(SIM_CONFIG_PATH)/$(SELECT_TEST_MK)
+include $(HCI_CONFIG_PATH)/hci_config.mk

config/hardware_config/hci_config.mk

@@ -0,0 +1,26 @@
+##############################
+# 		HCI parameters		 #
+##############################
+
+# Number of HWPEs attached to the port
+N_HWPE?=1
+# Width of an HWPE wide-word (as a multiple of DATA_WIDTH)
+HWPE_WIDTH?=4
+# Number of Core ports                                                  
+N_CORE?=8
+# Number of DMA ports                                                  
+N_DMA?=1
+# Number of External ports                                               
+N_EXT?=1
+# TEST_SET_BIT (for Log Interconnect)                   
+TS_BIT?=21
+# FIFO Depth for HWPE Interconnect                            
+EXPFIFO?=0
+# Log interconnect type selector
+SEL_LIC?=0
+# Width of DATA in bits                                                
+DATA_WIDTH?=32
+# Total memory size (kB)                                               
+TOT_MEM_SIZE?=32
+# Number of memory banks
+N_BANKS?=64

config/hardware_config/masters_config/hwpe0_config.mk

@@ -0,0 +1,18 @@
+###########################################
+#	  HWPE0 MEMORY ACCESS PARAMETERS	  #
+###########################################
+
+# Memory access type: 0 (random), 1 (linear), 2 (2D), 3 (3D)
+MEM_ACCESS_TYPE_HWPE0?=0
+# Starting address in binary (required for linear, 2D, and 3D accesses). Set to 0 if not needed
+START_ADDRESS_HWPE0?=0
+# Stride0 (required for linear, 2D, and 3D accesses). Set to 0 if not needed
+STRIDE0_HWPE0?=0
+# Len_d0 (required for 2D and 3D accesses). Set to 0 if not needed
+LEN_D0_HWPE0?=0
+# Stride1 (required for 2D and 3D accesses). Set to 0 if not needed
+STRIDE1_HWPE0?=0
+# Len_d1 (required for 3D accesses). Set to 0 if not needed
+LEN_D1_HWPE0?=0
+# Stride2 (required for 3D accesses). Set to 0 if not needed
+STRIDE2_HWPE0?=0

config/hardware_config/masters_config/log0_config.mk

@@ -0,0 +1,18 @@
+###########################################
+#	  LOG0 MEMORY ACCESS PARAMETERS		  #
+###########################################
+
+# Memory access type: 0 (random), 1 (linear), 2 (2D), 3 (3D)
+MEM_ACCESS_TYPE_LOG0?=0
+# Starting address in binary (required for linear, 2D, and 3D accesses). Set to 0 if not needed
+START_ADDRESS_LOG0?=0
+# Stride0 (required for linear, 2D, and 3D accesses). Set to 0 if not needed
+STRIDE0_LOG0?=0
+# Len_d0 (required for 2D and 3D accesses). Set to 0 if not needed
+LEN_D0_LOG0?=0
+# Stride1 (required for 2D and 3D accesses). Set to 0 if not needed
+STRIDE1_LOG0?=0
+# Len_d1 (required for 3D accesses). Set to 0 if not needed
+LEN_D1_LOG0?=0
+# Stride2 (required for 3D accesses). Set to 0 if not needed
+STRIDE2_LOG0?=0

config/hardware_config/masters_config/log1_config.mk

@@ -0,0 +1,18 @@
+###########################################
+#	  LOG1 MEMORY ACCESS PARAMETERS		  #
+###########################################
+
+# Memory access type: 0 (random), 1 (linear), 2 (2D), 3 (3D)
+MEM_ACCESS_TYPE_LOG1?=0
+# Starting address in binary (required for linear, 2D, and 3D accesses). Set to 0 if not needed
+START_ADDRESS_LOG1?=0
+# Stride0 (required for linear, 2D, and 3D accesses). Set to 0 if not needed
+STRIDE0_LOG1?=0
+# Len_d0 (required for 2D and 3D accesses). Set to 0 if not needed
+LEN_D0_LOG1?=0
+# Stride1 (required for 2D and 3D accesses). Set to 0 if not needed
+STRIDE1_LOG1?=0
+# Len_d1 (required for 3D accesses). Set to 0 if not needed
+LEN_D1_LOG1?=0
+# Stride2 (required for 3D accesses). Set to 0 if not needed
+STRIDE2_LOG1?=0

config/hardware_config/masters_config/log2_config.mk

@@ -0,0 +1,18 @@
+###########################################
+#	  LOG2 MEMORY ACCESS PARAMETERS		  #
+###########################################
+
+# Memory access type: 0 (random), 1 (linear), 2 (2D), 3 (3D)
+MEM_ACCESS_TYPE_LOG2?=0
+# Starting address in binary (required for linear, 2D, and 3D accesses). Set to 0 if not needed
+START_ADDRESS_LOG2?=0
+# Stride0 (required for linear, 2D, and 3D accesses). Set to 0 if not needed
+STRIDE0_LOG2?=0
+# Len_d0 (required for 2D and 3D accesses). Set to 0 if not needed
+LEN_D0_LOG2?=0
+# Stride1 (required for 2D and 3D accesses). Set to 0 if not needed
+STRIDE1_LOG2?=0
+# Len_d1 (required for 3D accesses). Set to 0 if not needed
+LEN_D1_LOG2?=0
+# Stride2 (required for 3D accesses). Set to 0 if not needed
+STRIDE2_LOG2?=0

config/hardware_config/masters_config/log3_config.mk

@@ -0,0 +1,18 @@
+###########################################
+#	  LOG3 MEMORY ACCESS PARAMETERS		  #
+###########################################
+
+# Memory access type: 0 (random), 1 (linear), 2 (2D), 3 (3D)
+MEM_ACCESS_TYPE_LOG3?=0
+# Starting address in binary (required for linear, 2D, and 3D accesses). Set to 0 if not needed
+START_ADDRESS_LOG3?=0
+# Stride0 (required for linear, 2D, and 3D accesses). Set to 0 if not needed
+STRIDE0_LOG3?=0
+# Len_d0 (required for 2D and 3D accesses). Set to 0 if not needed
+LEN_D0_LOG3?=0
+# Stride1 (required for 2D and 3D accesses). Set to 0 if not needed
+STRIDE1_LOG3?=0
+# Len_d1 (required for 3D accesses). Set to 0 if not needed
+LEN_D1_LOG3?=0
+# Stride2 (required for 3D accesses). Set to 0 if not needed
+STRIDE2_LOG3?=0