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Make the number of compare ports in id_queue parametric
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ricted98 committed Sep 9, 2024
1 parent 10dac0f commit edd31a2
Showing 1 changed file with 28 additions and 25 deletions.
53 changes: 28 additions & 25 deletions src/id_queue.sv
Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,7 @@ module id_queue #(
parameter int CAPACITY = 0,
parameter bit FULL_BW = 0,
parameter bit CUT_OUP_POP_INP_GNT = 0,
parameter int NUM_CMP_PORTS = 1,
parameter type data_t = logic[31:0],
// Dependent parameters, DO NOT OVERRIDE!
localparam type id_t = logic[ID_WIDTH-1:0]
Expand All @@ -62,11 +63,11 @@ module id_queue #(
input logic inp_req_i,
output logic inp_gnt_o,

input data_t exists_data_i,
input data_t exists_mask_i,
input logic exists_req_i,
output logic exists_o,
output logic exists_gnt_o,
input data_t [NUM_CMP_PORTS-1:0] exists_data_i,
input data_t [NUM_CMP_PORTS-1:0] exists_mask_i,
input logic [NUM_CMP_PORTS-1:0] exists_req_i,
output logic [NUM_CMP_PORTS-1:0] exists_o,
output logic [NUM_CMP_PORTS-1:0] exists_gnt_o,

input id_t oup_id_i,
input logic oup_pop_i,
Expand Down Expand Up @@ -118,8 +119,8 @@ module id_queue #(
idx_matches_in_id,
idx_matches_out_id;

logic [CAPACITY-1:0] exists_match,
linked_data_free;
logic [NUM_CMP_PORTS-1:0][CAPACITY-1:0] exists_match;
logic [CAPACITY-1:0] linked_data_free;

id_t match_in_id, match_out_id;

Expand Down Expand Up @@ -357,29 +358,31 @@ module id_queue #(
end

// Exists Lookup
for (genvar i = 0; i < CAPACITY; i++) begin: gen_lookup
data_t exists_match_bits;
for (genvar j = 0; j < $bits(data_t); j++) begin: gen_mask
always_comb begin
if (linked_data_q[i].free) begin
exists_match_bits[j] = 1'b0;
end else begin
if (!exists_mask_i[j]) begin
exists_match_bits[j] = 1'b1;
for (genvar k = 0; k < NUM_CMP_PORTS; k++) begin: gen_lookup_port
for (genvar i = 0; i < CAPACITY; i++) begin: gen_lookup
data_t exists_match_bits;
for (genvar j = 0; j < $bits(data_t); j++) begin: gen_mask
always_comb begin
if (linked_data_q[i].free) begin
exists_match_bits[j] = 1'b0;
end else begin
exists_match_bits[j] = (linked_data_q[i].data[j] == exists_data_i[j]);
if (!exists_mask_i[k][j]) begin
exists_match_bits[j] = 1'b1;
end else begin
exists_match_bits[j] = (linked_data_q[i].data[j] == exists_data_i[k][j]);

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[verible-verilog-lint] src/id_queue.sv#L372

Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]"  location:{path:"./src/id_queue.sv"  range:{start:{line:372  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
end
end
end
end
assign exists_match[k][i] = (&exists_match_bits);
end
assign exists_match[i] = (&exists_match_bits);
end
always_comb begin
exists_gnt_o = 1'b0;
exists_o = '0;
if (exists_req_i) begin
exists_gnt_o = 1'b1;
exists_o = (|exists_match);
always_comb begin
exists_gnt_o[k] = 1'b0;
exists_o[k] = '0;
if (exists_req_i[k]) begin
exists_gnt_o[k] = 1'b1;
exists_o[k] = (|exists_match[k]);
end
end
end

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