Update comment to describe moduole functionality

src/mem_multibank_pwrgate.sv

@@ -5,27 +5,29 @@
 // Lorenzo Leone <lleone@iis.ee.ethz.ch>
 
 // ## Description:
-//   A wrapper for `tc_sram_impl` which instantiate logic banks that can be in retentive mode
-//   or can be turned off. This module can be used for Power Aware simulations and the
-//   control signals can be driven directly from the UPF signals.
+//   A wrapper for `tc_sram_impl` that instantiates logic banks with retention mode
+//   or power-off capability.
+//   This module can be used for power-aware simulations, with control signals driven
+//   directly by UPF signals.
 //
 // ## Goal:
-//   In a memory with multiple banks and with power gate/retention capabilities, the addressing of
-//   each bank must be done in such a way that eventual interleaving is not broken.
-//   During retention or power off, only contiguos addresses should be switched.
-//   The memory, must be seen always as a set of contiguous addresses, without holes in the mapping.
+//   In a memory with multiple banks that support power gating and retention,
+//   each bank’s addressing must ensure that interleaving remains intact. During retention
+//   or power-off states, only contiguous addresses should be switched.
+//   The memory should always appear as a set of contiguous addresses, with no gaps in the
+//   address mapping.
+//   This module is responsible for managing the correct memory addressing
 //
-
 module mem_multibank_pwrgate #(
-    parameter int unsigned NumWords = 32'd1024,              // Number of Words in data array
-    parameter int unsigned DataWidth = 32'd128,              // Data signal width
-    parameter int unsigned ByteWidth = 32'd8,                // Width of a data byte
-    parameter int unsigned NumPorts = 32'd2,                 // Number of read and write ports
-    parameter int unsigned Latency = 32'd1,                  // Latency when the read data is available
-    parameter int unsigned NumLogicBanks = 32'd1,            // Logic bank for Power Management
-    parameter              SimInit = "none",                 // Simulation initialization
-    parameter bit          PrintSimCfg = 1'b0,               // Print configuration
-    parameter              ImplKey = "none",                 // Reference to specific implementation
+    parameter int unsigned NumWords = 32'd1024,                                   // Number of Words in data array
+    parameter int unsigned DataWidth = 32'd128,                                   // Data signal width
+    parameter int unsigned ByteWidth = 32'd8,                                     // Width of a data byte
+    parameter int unsigned NumPorts = 32'd2,                                      // Number of read and write ports
+    parameter int unsigned Latency = 32'd1,                                       // Latency when the read data is available
+    parameter int unsigned NumLogicBanks = 32'd1,                                 // Logic bank for Power Management
+    parameter              SimInit = "none",                                      // Simulation initialization
+    parameter bit          PrintSimCfg = 1'b0,                                    // Print configuration
+    parameter              ImplKey = "none",                                      // Reference to specific implementation
     // DEPENDENT PARAMETERS, DO NOT OVERWRITE!
     parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1,
     parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div
@@ -186,8 +188,10 @@ module mem_multibank_pwrgate #(
 `ifndef VERILATOR
 `ifndef TARGET_SYNTHESIS
    initial begin
-      assert (!$isunknown(deepsleep_i)) else $warning("deepsleep_i has some unconnected signals");
-      assert (!$isunknown(powergate_i)) else $warning("powergate_i has some unconnected signals");
+      assert (!$isunknown(deepsleep_i))
+      else $warning("deepsleep_i has some unconnected signals");
+      assert (!$isunknown(powergate_i))
+      else $warning("powergate_i has some unconnected signals");
    end
 `endif
 `endif