[HW] Bump CVA6 to pulp-v2

Bender.lock

@@ -7,8 +7,8 @@ packages:
     dependencies:
     - common_cells
   axi:
-    revision: 587355b77b8ce94dcd600efbd5d5bd118ff913a7
-    version: 0.39.4
+    revision: 853ede23b2a9837951b74dbdc6d18c3eef5bac7d
+    version: 0.39.5
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
@@ -30,7 +30,7 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   cva6:
-    revision: feb5f72b5cafb840388ea85b155dfb4013c1926f
+    revision: 4415e7142810ff4b7351935ac1f73986a32b99ac
     version: null
     source:
       Git: https://github.com/pulp-platform/cva6.git
@@ -40,7 +40,7 @@ packages:
     - fpnew
     - tech_cells_generic
   fpnew:
-    revision: f231041c610f270ffc03cbdac38739ddb6426572
+    revision: de4f932e6d00951c092d38567da07e66a0f5865e
     version: null
     source:
       Git: https://github.com/pulp-platform/cvfpu.git

Bender.yml

@@ -10,7 +10,7 @@ package:
 dependencies:
   axi:                { git: "https://github.com/pulp-platform/axi.git",                version: 0.39.1                               }
   common_cells:       { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.22.1                               }
-  cva6:               { git: "https://github.com/pulp-platform/cva6.git",               rev: feb5f72b5cafb840388ea85b155dfb4013c1926f } # mp/pulp-v1-araOS
+  cva6:               { git: "https://github.com/pulp-platform/cva6.git",               rev: 4415e7142810ff4b7351935ac1f73986a32b99ac } # mp/pulp-v2
   tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13                               }
   apb:                { git: "https://github.com/pulp-platform/apb.git",                version: 0.2.4                                }
 
@@ -69,6 +69,7 @@ sources:
     - target: ara_test
       files:
         # Level 1
+        - hardware/deps/cva6/corev_apu/tb/common/mock_uart.sv
         - hardware/tb/ara_testharness.sv
         # Level 2
         - hardware/tb/ara_tb.sv

CHANGELOG.md

@@ -67,6 +67,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
  - Refactor MASKU
  - Remove bit-support for tail elements
  - Adapt mask tests to this behavior
+ - Bump CVA6 to pulp-v2
+ - Re-parametrize the design with pulp-v2 parameters
 
 ## 3.0.0 - 2023-09-08
 

hardware/Makefile

@@ -54,7 +54,7 @@ top_level      ?= ara_tb
 ifeq ($(vcd_dump), 1)
   questa_version ?= 2019.3
 else
-  questa_version ?= 2021.2
+  questa_version ?= 2021.3
 endif
 # QuestaSim command
 questa_cmd     ?= questa-$(questa_version)
@@ -109,7 +109,7 @@ vlog_args += -work $(library)
 bender_defs += --define NR_LANES=$(nr_lanes) --define VLEN=$(vlen) --define ARIANE_ACCELERATOR_PORT=1
 bender_defs_veril := $(bender_defs) --define COMMON_CELLS_ASSERTS_OFF
 # Targets
-bender_common_targs := -t rtl -t cv64a6_imafdcv_sv39 -t tech_cells_generic_include_tc_sram -t tech_cells_generic_include_tc_clk
+bender_common_targs := -t rtl -t cv64a6_imafdcv_sv39 -t tech_cells_generic_include_tc_sram -t tech_cells_generic_include_tc_clk -t exclude_first_pass_decoder
 bender_targs_simc     := $(bender_common_targs) -t ara_test -t cva6_test
 bender_targs_veril    := $(bender_common_targs) -t ara_test -t cva6_test -t verilator
 bender_targs_spyglass := $(bender_common_targs) -t spyglass

hardware/include/ara_pkg.sv

@@ -293,13 +293,7 @@ package ara_pkg;
   //  Accelerator interface  //
   /////////////////////////////
 
-  // Use Ariane's accelerator interface.
-  typedef acc_pkg::cva6_to_acc_t cva6_to_acc_t;
-  typedef acc_pkg::acc_to_cva6_t acc_to_cva6_t;
-  typedef acc_pkg::accelerator_req_t accelerator_req_t;
-  typedef acc_pkg::accelerator_resp_t accelerator_resp_t;
-  typedef acc_pkg::acc_mmu_req_t acc_mmu_req_t;
-  typedef acc_pkg::acc_mmu_resp_t acc_mmu_resp_t;
+  // See CVA6 and Ara main modules
 
   ////////////////////
   //  PE interface  //

hardware/src/accel_dispatcher_ideal.sv

@@ -20,7 +20,12 @@
 `define N_VINSN 1
 `endif
 
-module accel_dispatcher_ideal import axi_pkg::*; import ara_pkg::*; (
+module accel_dispatcher_ideal import axi_pkg::*; import ara_pkg::*; # (
+  parameter  config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg,
+  parameter type accelerator_req_t  = logic,
+  parameter type accelerator_resp_t = logic,
+  localparam type xlen_t = logic [CVA6Cfg.XLEN-1:0]
+) (
   input logic                     clk_i,
   input logic                     rst_ni,
   // Accelerator interaface
@@ -40,8 +45,8 @@ module accel_dispatcher_ideal import axi_pkg::*; import ara_pkg::*; (
 
   typedef struct packed {
     riscv::instruction_t insn;
-    riscv::xlen_t rs1;
-    riscv::xlen_t rs2;
+    xlen_t rs1;
+    xlen_t rs2;
   } fifo_payload_t;
 
   logic [DATA_WIDTH-1:0] fifo_data_raw;
@@ -154,7 +159,7 @@ endmodule
 
     typedef struct packed {
       riscv::instruction_t insn;
-      riscv::xlen_t rs1;
+      xlen_t rs1;
     } fifo_payload_t;
     fifo_payload_t payload;
 

hardware/src/ara.sv

@@ -17,6 +17,8 @@ module ara import ara_pkg::*; #(
     parameter  fpext_support_e        FPExtSupport = FPExtSupportEnable,
     // Support for fixed-point data types
     parameter  fixpt_support_e        FixPtSupport = FixedPointEnable,
+    // CVA6 configuration
+    parameter  config_pkg::cva6_cfg_t CVA6Cfg      = cva6_config_pkg::cva6_cfg,
     // AXI Interface
     parameter  int           unsigned AxiDataWidth = 0,
     parameter  int           unsigned AxiAddrWidth = 0,
@@ -32,7 +34,66 @@ module ara import ara_pkg::*; #(
     // vector store unit, the slide unit, and the mask unit.
     localparam int           unsigned NrPEs        = NrLanes + 4,
     localparam type                   vlen_t       = logic[$clog2(VLEN+1)-1:0],
-    localparam int           unsigned VLENB        = VLEN / 8
+    localparam int           unsigned VLENB        = VLEN / 8,
+    // Exception type: should be the same as in CVA6
+    localparam type exception_t = struct packed {
+      logic [CVA6Cfg.XLEN-1:0] cause;  // cause of exception
+      logic [CVA6Cfg.XLEN-1:0] tval;  // additional information of causing exception (e.g.: instruction causing it),
+      // address of LD/ST fault
+      logic [CVA6Cfg.GPLEN-1:0] tval2;  // additional information when the causing exception in a guest exception
+      logic [31:0] tinst;  // transformed instruction information
+      logic gva;  // signals when a guest virtual address is written to tval
+      logic valid;
+    },
+    // Interfaces (they need the CVA6Cfg)
+	localparam type acc_mmu_req_t = struct packed {
+      logic                    acc_mmu_misaligned_ex;
+      logic                    acc_mmu_req;
+      logic [CVA6Cfg.VLEN-1:0] acc_mmu_vaddr;
+      logic                    acc_mmu_is_store;
+    },
+    localparam type acc_mmu_resp_t = struct packed {
+      logic                    acc_mmu_dtlb_hit;
+      logic [CVA6Cfg.PPNW-1:0] acc_mmu_dtlb_ppn;
+      logic                    acc_mmu_valid;
+      logic [CVA6Cfg.PLEN-1:0] acc_mmu_paddr;
+      exception_t              acc_mmu_exception;
+    },
+    localparam type accelerator_req_t = struct packed {
+      logic                             req_valid;
+      logic                             resp_ready;
+      riscv::instruction_t              insn;
+      logic [CVA6Cfg.XLEN-1:0]          rs1;
+      logic [CVA6Cfg.XLEN-1:0]          rs2;
+      fpnew_pkg::roundmode_e            frm;
+      logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id;
+      logic                             store_pending;
+      logic                             acc_cons_en; // Invalidation interface
+      logic                             inval_ready; // Invalidation interface
+    },
+    localparam type accelerator_resp_t = struct packed {
+      logic                                 req_ready;
+      logic                                 resp_valid;
+      logic [CVA6Cfg.XLEN-1:0]              result;
+      logic [CVA6Cfg.TRANS_ID_BITS-1:0]     trans_id;
+      exception_t                           exception;
+      logic                                 store_pending;
+      logic                                 store_complete;
+      logic                                 load_complete;
+      logic [4:0]                           fflags;
+      logic                                 fflags_valid;
+      logic                                 inval_valid; // Invalidation interface
+      logic [63:0]                          inval_addr; // Invalidation interface
+    },
+    localparam type cva6_to_acc_t = struct packed {
+      accelerator_req_t                     acc_req; // Insn/mem
+      logic                                 acc_mmu_en; // MMU
+      acc_mmu_resp_t                        acc_mmu_resp; // MMU
+    },
+    localparam type acc_to_cva6_t = struct packed {
+      accelerator_resp_t                    acc_resp; // Insn/mem
+      acc_mmu_req_t                         acc_mmu_req; // MMU
+    }
   ) (
     // Clock and Reset
     input  logic              clk_i,
@@ -145,7 +206,7 @@ module ara import ara_pkg::*; #(
     elen_t resp;
 
     // Instruction triggered an exception
-    ariane_pkg::exception_t exception;
+    exception_t exception;
 
     // New value for vstart
     vlen_t exception_vstart;
@@ -174,10 +235,13 @@ module ara import ara_pkg::*; #(
   vxrm_t     [NrLanes-1:0]      alu_vxrm;
 
   ara_dispatcher #(
-    .NrLanes   (NrLanes   ),
-    .VLEN      (VLEN      ),
-    .ara_req_t (ara_req_t ),
-    .ara_resp_t(ara_resp_t)
+    .NrLanes          (NrLanes            ),
+    .VLEN             (VLEN               ),
+    .CVA6Cfg          (CVA6Cfg            ),
+    .ara_req_t        (ara_req_t          ),
+    .ara_resp_t       (ara_resp_t         ),
+    .accelerator_req_t(accelerator_req_t  ),
+    .accelerator_resp_t(accelerator_resp_t)
   ) i_dispatcher (
     .clk_i             (clk_i           ),
     .rst_ni            (rst_ni          ),
@@ -215,7 +279,7 @@ module ara import ara_pkg::*; #(
   pe_resp_t          [NrPEs-1:0]   pe_resp;
   // Interface with the address generator
   logic                            addrgen_ack;
-  ariane_pkg::exception_t          addrgen_exception;
+  exception_t                      addrgen_exception;
   vlen_t                           addrgen_exception_vstart;
   logic              [NrLanes-1:0] alu_vinsn_done;
   logic              [NrLanes-1:0] mfpu_vinsn_done;
@@ -238,12 +302,13 @@ module ara import ara_pkg::*; #(
   logic      result_scalar_valid;
 
   ara_sequencer #(
-    .NrLanes   (NrLanes   ),
-    .VLEN      (VLEN      ),
-    .ara_req_t (ara_req_t ),
-    .ara_resp_t(ara_resp_t),
-    .pe_req_t  (pe_req_t  ),
-    .pe_resp_t (pe_resp_t )
+    .NrLanes    (NrLanes   ),
+    .VLEN       (VLEN      ),
+    .ara_req_t  (ara_req_t ),
+    .ara_resp_t (ara_resp_t),
+    .pe_req_t   (pe_req_t  ),
+    .pe_resp_t  (pe_resp_t ),
+    .exception_t(exception_t)
   ) i_sequencer (
     .clk_i                 (clk_i                    ),
     .rst_ni                (rst_ni                   ),
@@ -413,10 +478,10 @@ module ara import ara_pkg::*; #(
 
   // Optional OS support
   logic acc_mmu_misaligned_ex, acc_mmu_req, acc_mmu_is_store, acc_mmu_dtlb_hit, acc_mmu_valid, acc_mmu_en;
-  logic [riscv::VLEN-1:0] acc_mmu_vaddr;
-  logic [riscv::PLEN-1:0] acc_mmu_paddr;
-  logic [riscv::PPNW-1:0] acc_mmu_dtlb_ppn;
-  ariane_pkg::exception_t acc_mmu_exception;
+  logic [CVA6Cfg.VLEN-1:0] acc_mmu_vaddr;
+  logic [CVA6Cfg.PLEN-1:0] acc_mmu_paddr;
+  logic [CVA6Cfg.PPNW-1:0] acc_mmu_dtlb_ppn;
+  exception_t acc_mmu_exception;
   if (OSSupport) begin
     assign acc_resp_o.acc_mmu_req.acc_mmu_misaligned_ex = acc_mmu_misaligned_ex;
     assign acc_resp_o.acc_mmu_req.acc_mmu_req           = acc_mmu_req;
@@ -455,7 +520,9 @@ module ara import ara_pkg::*; #(
     .axi_resp_t  (axi_resp_t  ),
     .vaddr_t     (vaddr_t     ),
     .pe_req_t    (pe_req_t    ),
-    .pe_resp_t   (pe_resp_t   )
+    .pe_resp_t   (pe_resp_t   ),
+    .CVA6Cfg     (CVA6Cfg     ),
+    .exception_t (exception_t )
   ) i_vlsu (
     .clk_i                      (clk_i                                                 ),
     .rst_ni                     (rst_ni                                                ),

hardware/src/ara_dispatcher.sv

@@ -9,10 +9,15 @@
 // response or an error message.
 
 module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
-    parameter int           unsigned NrLanes      = 0,
-    parameter int           unsigned VLEN         = 0,
-    parameter type                   ara_req_t    = logic,
-    parameter type                   ara_resp_t   = logic,
+    parameter int           unsigned NrLanes            = 0,
+    parameter int           unsigned VLEN               = 0,
+    parameter type                   ara_req_t          = logic,
+    parameter type                   ara_resp_t         = logic,
+    parameter type                   accelerator_req_t  = logic,
+    parameter type                   accelerator_resp_t = logic,
+    // CVA6 configuration
+    parameter config_pkg::cva6_cfg_t CVA6Cfg      = cva6_config_pkg::cva6_cfg,
+    localparam type                  xlen_t       = logic [CVA6Cfg.XLEN-1:0],
     // Support for floating-point data types
     parameter fpu_support_e          FPUSupport   = FPUSupportHalfSingleDouble,
     // External support for vfrec7, vfrsqrt7
@@ -71,15 +76,15 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
   `FF(csr_vxsat_q, csr_vxsat_d, '0)
   `FF(csr_vxrm_q, csr_vxrm_d, '0)
   // Converts between the internal representation of `vtype_t` and the full XLEN-bit CSR.
-  function automatic riscv::xlen_t xlen_vtype(vtype_t vtype);
-    xlen_vtype = {vtype.vill, {riscv::XLEN-9{1'b0}}, vtype.vma, vtype.vta, vtype.vsew,
+  function automatic xlen_t xlen_vtype(vtype_t vtype);
+    xlen_vtype = {vtype.vill, {CVA6Cfg.XLEN-9{1'b0}}, vtype.vma, vtype.vta, vtype.vsew,
       vtype.vlmul[2:0]};
   endfunction: xlen_vtype
 
   // Converts between the XLEN-bit vtype CSR and its internal representation
-  function automatic vtype_t vtype_xlen(riscv::xlen_t xlen);
+  function automatic vtype_t vtype_xlen(xlen_t xlen);
     vtype_xlen = '{
-      vill  : xlen[riscv::XLEN-1],
+      vill  : xlen[CVA6Cfg.XLEN-1],
       vma   : xlen[7],
       vta   : xlen[6],
       vsew  : vew_e'(xlen[5:3]),
@@ -492,11 +497,11 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
 
                 // Update vtype
                 if (insn.vsetvli_type.func1 == 1'b0) begin // vsetvli
-                  csr_vtype_d = vtype_xlen(riscv::xlen_t'(insn.vsetvli_type.zimm11));
+                  csr_vtype_d = vtype_xlen(xlen_t'(insn.vsetvli_type.zimm11));
                 end else if (insn.vsetivli_type.func2 == 2'b11) begin // vsetivli
-                  csr_vtype_d = vtype_xlen(riscv::xlen_t'(insn.vsetivli_type.zimm10));
+                  csr_vtype_d = vtype_xlen(xlen_t'(insn.vsetivli_type.zimm10));
                 end else if (insn.vsetvl_type.func7 == 7'b100_0000) begin // vsetvl
-                  csr_vtype_d = vtype_xlen(riscv::xlen_t'(acc_req_i.rs2[7:0]));
+                  csr_vtype_d = vtype_xlen(xlen_t'(acc_req_i.rs2[7:0]));
                 end else
                   illegal_insn = 1'b1;
 

hardware/src/ara_sequencer.sv

@@ -9,12 +9,13 @@
 
 module ara_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::idx_width; #(
     // RVV Parameters
-    parameter  int unsigned NrLanes    = 1,          // Number of parallel vector lanes
-    parameter  int unsigned VLEN       = 0,
-    parameter  type         ara_req_t  = logic,
-    parameter  type         ara_resp_t = logic,
-    parameter  type         pe_req_t   = logic,
-    parameter  type         pe_resp_t  = logic,
+    parameter  int unsigned NrLanes     = 1,          // Number of parallel vector lanes
+    parameter  int unsigned VLEN        = 0,
+    parameter  type         ara_req_t   = logic,
+    parameter  type         ara_resp_t  = logic,
+    parameter  type         pe_req_t    = logic,
+    parameter  type         pe_resp_t   = logic,
+    parameter  type         exception_t = logic,
     // Dependant parameters. DO NOT CHANGE!
     // Ara has NrLanes + 3 processing elements: each one of the lanes, the vector load unit, the
     // vector store unit, the slide unit, and the mask unit.
@@ -46,7 +47,7 @@ module ara_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::i
     output logic                            pe_scalar_resp_ready_o,
     // Interface with the Address Generation
     input  logic                            addrgen_ack_i,
-    input  ariane_pkg::exception_t          addrgen_exception_i,
+    input  exception_t                      addrgen_exception_i,
     input  vlen_t                           addrgen_exception_vstart_i
   );