@mp-17 @suehtamacv Hello, we have made certain changes based on ARA, including single-lane versions, multi-lane versions, and performance optimizations. One perspective on the reshuffle mechanism is that under the current multi-lane architecture, VRF and computation are spread across each lane, but when a single sew changes, data from lane #1 may need to be moved to lane #0, such as switching from sew8 to sew16. However, when ARA switches between source and destination operands (SEW), it needs to insert the reshuffle instruction, i.e., slide.
However, there is a fatal flaw here: if a vle8 instruction is used under e8m8 to fill v0 to v31, then switching to e16m1 and using vwadd v0, v1, v4 will cause a hang, because eew_v1 is e16, while eew_v0 to v1 is e32. This will result in the dispatcher module alternating between reshuffle and normal states, and v1 cannot be stabilized in the eew_q state.
Based on the above issues, I made some modifications for future modifications. All reshuffles are only applied to vd, while VS reshuffles are performed at the VRF outlet. For example, the vwadd instruction only reshuffles v0~v1 to the e32 state, while transmitting eew_q to the next stage. When reading VRF, src_eew_before and src_eew_after can be passed. Then use the global module to reshuffle all lane value. Finally, distribute the vs after reshuffle to different lanes. This can also significantly reduce the problem of increasing the actual number of instructions caused by reshuffle
However, even if you only reshuffle on vd with non-full vl, frequent reshuffles will still affect performance. I wonder if you have better solutions？
Thanks
@mp-17 @suehtamacv Hello, we have made certain changes based on ARA, including single-lane versions, multi-lane versions, and performance optimizations. One perspective on the reshuffle mechanism is that under the current multi-lane architecture, VRF and computation are spread across each lane, but when a single sew changes, data from lane #1 may need to be moved to lane #0, such as switching from sew8 to sew16. However, when ARA switches between source and destination operands (SEW), it needs to insert the reshuffle instruction, i.e., slide.
However, there is a fatal flaw here: if a vle8 instruction is used under e8m8 to fill v0 to v31, then switching to e16m1 and using vwadd v0, v1, v4 will cause a hang, because eew_v1 is e16, while eew_v0 to v1 is e32. This will result in the dispatcher module alternating between reshuffle and normal states, and v1 cannot be stabilized in the eew_q state.
Based on the above issues, I made some modifications for future modifications. All reshuffles are only applied to vd, while VS reshuffles are performed at the VRF outlet. For example, the vwadd instruction only reshuffles v0~v1 to the e32 state, while transmitting eew_q to the next stage. When reading VRF, src_eew_before and src_eew_after can be passed. Then use the global module to reshuffle all lane value. Finally, distribute the vs after reshuffle to different lanes. This can also significantly reduce the problem of increasing the actual number of instructions caused by reshuffle
However, even if you only reshuffle on vd with non-full vl, frequent reshuffles will still affect performance. I wonder if you have better solutions？
Thanks