Failed in RTL Simulation #314
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Hello @Tanishqgithub, Provided that you have already installed Verilator and run # Compile fmatmul for Ara
make -C apps bin/fmatmul
# Verilate the design
make -C hardware verilate
# Run fmatmul on Ara through Verilator
make -C hardware simv app=fmatmul |
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It seems that
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i got the following o/p :
If my command is working fine please tell me what are the next final commands after this step of command and why is there in finding the QuestaSim Version and the deps : No such file or directory
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For the compilation, there was a typo in my command, sorry. You should first give: make -C apps bin/fmatmulThen, it seems you also have a problem with Verilator. sh: 1: exec: /home/tanishq/Documents/ARAnew/ara/install/verilator/share/verilator/verilator_bin: not found
%Error: Command Failed ulimit -s unlimited 2>/dev/null; exec /home/tanishq/Documents/ARAnew/ara/install/verilator/share/verilator/verilator_bin -fI am not sure why you get this. You can first try to re-install a fresh version of Verilator and check that you have not got any errors while installing it. Before installing it, be sure that If the issue is not solved, you can ask for support in the Verilator repository. Otherwise, if you can access QuestaSim, you can simulate with it by replacing |
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As per your suggestion i tried out to re-install verilator using the command but after i run i got the following o/p which is same as previous situation : Can you please help me solving this issue and this time i didn't run |
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Yes, you can skip For Verilator, this seems the "interesting" error: There is something problematic with your verilator setup. Try attaching the .log from when you installed verilator with Ideally, |
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My typo. The command should be: Do you have the full log of the make command when you issue |
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That seems okay. This is also okay. If you want to access the clang you installed with the ./install/riscv-llvm/bin/clang --versionWhen you install verilator from scratch, you can do: make verilator |& tee verilator_install.logOr, if you don't have make verilator &> verilator_install.log |
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Respected sir I re-clonned the entire setup and tried to start from first :
i ran this command
O/p :
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Does the following command work? The problem remains the Verilator installation, but I don't see errors in the log and unluckily I don't know why the executable is searched in: You can try to patch the reference this way, but I don't think it will work: mkdir -p /home/tanishq/Documents/ARA_new/ara/install/verilator/share/verilator
ln -s /home/tanishq/Documents/ARA_new/ara/install/verilator/bin/verilator_bin /home/tanishq/Documents/ARA_new/ara/install/verilator/share/verilator/verilator_binYou need a license to use QuestaSim; if you have not one, you need to use Verilator |
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Do you have If not: If it still cannot find the header after installing libelf, we need to explicitly tell |
and got the following o/p : But i couldn't see the .vcd file in location
and i got the following error : Can you please tell me what step i am going wrong to generate .vcd file and .fst file |
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Respected sir
A kind request to reply for the last query
Thanking you
Tanishq.S
…On Mon, 1 Jul, 2024, 7:37 pm Matteo Perotti, ***@***.***> wrote:
Do you have libelf installed?
If not:
apt-get install libelf-dev
If it still cannot find the header after installing libelf, we need to
explicitly tell clang++ where to find it.
—
Reply to this email directly, view it on GitHub
<#314 (comment)>,
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You are receiving this because you were mentioned.Message ID:
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I have never tried to bump .vcd files with verilator. However, you can try with the full path to a file, not a directory: make -C hardware simv app=fmatmul vcd_dump=1 vcd_path=$/home/tanishq/Documents/ARA_new/ara/fmatmul.vcdRegarding the verilator trace, you should verilate the design again: make -C hardware verilate trace=1 -B |
There is no output
For the command : i got this error : |
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For the For the vcd file I will need more time to check |
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@mp-17 |
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I am not sure why this happens, I will need to debug this as soon as I have time :-) |
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For fst i tried the solution in #260 i,e changing -O3 to -O0 but the simulation sort of stopped midway and gave this o/p : and while viewing sim.fst in terminal : and by manually opening the sim.fst in the file location i could see only signals of CVA6
Can you please tell me how to encounter this issue and if the solution is bumping down the verilator version then please tell me what is the solution for the error i am occuring. |
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@mp-17 A kind request to reply for the last query Thanking you |
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I did bump down the verilator version to 4.214 and i tried the fst simulation : i got this o/p in terminal : and then i tried to open sim.fst in Am i getting the correct |
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Can you please update on the |
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Respected sir
I am working on Oracle virtual box with Ubuntu 22.04 LTS version
I ran the prerequisite dependency commands which gave some 404 error but was overcome using the --fix-missing
cloned the repository along with the submodules
make toolchain-llvm [abnormally there were some "failed" for tests when we run this]
a. Is that ok ?
b. i sense something wrong in my clang installation [please see "clang.png" , the path is not printed]
make riscv-isa-sim [no problem running it]
make verilator [no problem running it after running
sudo apt-get install libstdc++-12-dev]tried running other "apps" other than hello_world like fmatmul and got o/p as in "fmatmul.txt"
a. Why is the number of cycles 0 and performance is also not computed ?
b. In this step is the application running on the vector processor designed only? because not integrated with CVA6 till now ..
fmatmul.txt
make riscv_tests :
a. solved after running
make toolchain-gccfrom RTL Simulation of README :
a. tried running make checkout but got the error message in "make_checkout.png"
b. please guide from this step
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