Initial release

.gitattributes

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+*.onnx filter=lfs diff=lfs merge=lfs -text
+*.npz filter=lfs diff=lfs merge=lfs -text
+*.npy filter=lfs diff=lfs merge=lfs -text
+*.zip filter=lfs diff=lfs merge=lfs -text

.gitignore

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+modelsim/build*
+modelsim/work/
+modelsim/wlft*
+simvectors/
+.bender/
+
+# Byte-compiled / optimized / DLL files
+__pycache__/
+*.py[cod]
+*$py.class
+
+*~
+build
+dist
+**/DumpO.egg*
+
+*venv
+
+.DS_Store
+*.html
+
+# Jupyter Notebook
+.ipynb_checkpoints
+
+# Ignore everything in .vscode except launch.json
+.vscode/*
+!.vscode/launch.json
+!.vscode/settings.json
+!.vscode/c_cpp_properties.json
+
+simvectors
+install
+**/quantlib
+
+logs
+
+# Ignore Bender dependencies
+deps
+

.gitlab-ci.yml

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+# Copyright 2023 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+variables:
+  GIT_SUBMODULE_STRATEGY: recursive
+
+stages:
+  - test
+  - sim
+
+.setup_test:
+  script:
+    - python -m venv venv
+    - source venv/bin/activate
+    - pip install -r requirements.txt
+
+format_python:
+  stage: test
+  script:
+    - !reference [.setup_test, script]
+    - pip install yapf
+    - yapf -rpd .
+
+generate_testvectors:
+  stage: test
+  script:
+    - !reference [.setup_test, script]
+    - python testGenerator.py -H 1 -S 64 -E 64 -P 64
+    - python testGenerator.py -H 1 -S 128 -E 192 -P 256
+  artifacts:
+    paths:
+      - simvectors
+    expire_in: 1 day
+
+run_sim:
+  stage: sim
+  needs:
+    - generate_testvectors
+  parallel:
+    matrix:
+    - S: 64
+      E: 64
+      P: 64
+    - S: 128
+      E: 192
+      P: 256
+  script:
+    - make bender
+    - make sim VSIM_FLAGS=-c s=$S e=$E p=$P bias=1
+    - ./modelsim/return_status.sh modelsim/build/transcript $S $E ita_tb
+
+run_hwpe_sim:
+  stage: sim
+  needs:
+    - generate_testvectors
+  parallel:
+    matrix:
+    - S: 64
+      E: 64
+      P: 64
+    - S: 128
+      E: 192
+      P: 256
+  script:
+    - make bender
+    - make sim VSIM_FLAGS=-c DEBUG=OFF target=sim_ita_hwpe_tb s=$S e=$E p=$P bias=1
+    - ./modelsim/return_status.sh modelsim/build/transcript $S $E hwpe_tb

.style.yapf

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+[style]
+based_on_style = google
+column_limit = 120
+split_before_logical_operator = true
+spaces_around_default_or_named_assign = true

.vscode/launch.json

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+{
+    // Use IntelliSense to learn about possible attributes.
+    // Hover to view descriptions of existing attributes.
+    // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
+    "version": "0.2.0",
+    "configurations": [
+        {
+            "name": "Generate Test",
+            "type": "python",
+            "request": "launch",
+            "program": "${workspaceFolder}/testGenerator.py",
+            "console": "integratedTerminal",
+            "cwd": "${workspaceFolder}",
+            "justMyCode": false,
+            "args": [
+                "-H${input:heads}",
+                "-S${input:seq_len}",
+                "-E${input:emb_len}",
+                "-P${input:prj_len}",
+            ],
+        }
+    ],
+    "inputs": [
+        {
+            "id": "heads",
+            "type": "promptString",
+            "description": "Number of heads",
+            "default": "1"
+        },
+        {
+            "id": "seq_len",
+            "type": "promptString",
+            "description": "Sequence length",
+            "default": "64"
+        },
+        {
+            "id": "emb_len",
+            "type": "promptString",
+            "description": "Embenbing length",
+            "default": "64"
+        },
+        {
+            "id": "prj_len",
+            "type": "promptString",
+            "description": "Projection length",
+            "default": "64"
+        }
+    ]
+}

.yapfignore

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+*third_party/
+*venv/
+*simvectors/

Bender.local

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+# Copyright 2023 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+overrides:
+    hwpe-stream: { git: "https://github.com/pulp-platform/hwpe-stream.git", rev: "a20f35e62fe2842904797079dc7881e490ff7117" }

Bender.yml

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+# Copyright 2023 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+# Package metadata. Required.
+package:
+  # The name of the package. Required.
+  name: ita
+
+  # The list of package authors and contributors. Optional.
+  # By convention, authors should be listed in the form shown below.
+  authors: 
+    - Gamze Islamoglu <gislamoglu@iis.ee.ethz.ch>
+    - Philip Wiese <wiesep@iis.ee.ethz.ch>
+
+# Other packages this package depends on. Optional.
+dependencies:
+  common_cells:       { git: https://github.com/pulp-platform/common_cells, version: 1.23.0 }
+  hwpe-stream:        { git: https://github.com/pulp-platform/hwpe-stream, rev: a20f35e62fe2842904797079dc7881e490ff7117 }
+  hci:                { git: https://github.com/pulp-platform/hci, rev: 066c7ce7d24b61587e245decb592054669d7a2d1 }
+  hwpe-ctrl:          { git: https://github.com/pulp-platform/hwpe-ctrl, rev: 2926867cafb3fb518a1ae849675f281b79ecab8a }
+  scm:                { git: https://github.com/pulp-platform/scm, rev: 998466d2a3c2d7d572e43d2666d93c4f767d8d60 }
+  tech_cells_generic: { git: https://github.com/pulp-platform/tech_cells_generic, version:  0.2.11 }
+
+# Freeze any dependency updates. Optional. False if omitted.
+# Useful for chip packages. Once the chip is in final tapeout mode, and
+# dependency updates would require disastrous amounts of re-verification.
+frozen: false
+
+# List of source files in this package. Optional.
+sources:
+  # Individual source files are simple string entries:
+  - src/ita_package.sv
+  - src/ita_accumulator.sv
+  - src/ita_controller.sv
+  - src/ita_dotp.sv
+  - src/ita_fifo_controller.sv
+  - src/ita_inp1_mux.sv
+  - src/ita_inp2_mux.sv
+  - src/ita_input_sampler.sv
+  - src/ita_output_controller.sv
+  - src/ita_register_file_1w_1r_double_width_write.sv
+  - src/ita_register_file_1w_multi_port_read.sv
+  - src/ita_register_file_1w_multi_port_read_we.sv
+  - src/ita_requantizer.sv
+  - src/ita_serdiv.sv
+  - src/ita_softmax.sv
+  - src/ita_softmax_top.sv
+  - src/ita_sumdotp.sv
+  - src/ita_weight_controller.sv
+  - src/ita.sv
+  - src/ita_max_finder.sv
+
+  # HWPE sources
+  - target: hwpe
+    files:
+      - src/hwpe/ita_hwpe_package.sv
+      - src/hwpe/ita_hwpe_ctrl.sv
+      - src/hwpe/ita_hwpe_engine.sv
+      - src/hwpe/ita_hwpe_input_buffer.sv
+      - src/hwpe/ita_hwpe_input_bias_buffer.sv
+      - src/hwpe/ita_hwpe_input_bias_fence.sv
+      - src/hwpe/ita_hwpe_output_buffer.sv
+      - src/hwpe/ita_hwpe_streamer.sv
+      - src/hwpe/ita_hwpe_top.sv
+      - src/hwpe/ita_hwpe_wrap.sv
+
+  # Level 1
+  # TB sources
+  - target: test
+    files:
+      - src/tb/ita_tb.sv
+      - src/tb/clk_rst_gen.sv
+      - src/tb/rst_gen.sv
+
+  # HWPE TB sources
+  - target: hwpe_test
+    files:
+      - src/hwpe/tb/tb_dummy_memory.sv
+      - src/hwpe/tb/ita_hwpe_tb.sv