VLSI Subscalar Computation Implementation

Implementation of Figure 1 (parallel-prefix) and Figure 2 (subscalar) adder architectures from the paper.

Architecture Comparison

Figure 1 - Parallel-Prefix Adder:

• 4-stage pipeline with 8-bit grouping
• High area cost, deeply pipelined
• Takes ~10 cycles for s = a + b + c

Figure 2 - Subscalar Adder:

• Fragment-based with 8-bit ripple blocks
• Registers between fragments enable overlap
• Takes ~5 cycles for s = a + b + c

Files

• ParallelPrefixAdder.scala - Figure 1 implementation
• SubscalarAdder.scala - Figure 2 implementation
• TestBench.scala - Top-level with both architectures
• testbench.v - Verilog testbench
• run_sim.sh - Automated simulation script

Usage

# Run complete simulation
./run_sim.sh

# Manual steps:
sbt "runMain VerilogGen"
cd generated
iverilog -o sim ../testbench.v Top.v
./sim
gtkwave waveform.vcd

Key Differences Demonstrated

1. Latency: Subscalar completes dependent additions faster
2. Area: Fewer pipeline registers in subscalar design
3. Throughput: Fragment-level parallelism in subscalar approach