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clk: samsung: gs101: propagate PERIC0 USI SPI clock rate
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Introduce nMUX() for MUX clocks that can be reparented on clock rate
change. "nMUX" comes from "n-to-1 selector", hopefully emphasising that
the selector can change on clock rate changes. Ideally MUX/MUX_F()
should change to not have the CLK_SET_RATE_NO_REPARENT flag set by
default, and all their users to be updated to add the flag back
(like in the case of DIV and GATE). But this is a very intrusive change
and because for now only GS101 allows MUX reparenting on clock rate
change, stick with nMUX().

GS101 defines MUX clocks that are dedicated for each instance of the IP.
One example is USI IP (SPI, I2C, serial). The reparenting of these MUX
clocks will not affect other instances of the same IP or different IPs
altogether.

When SPI transfer is being prepared, the spi-s3c64xx driver will call
clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK
is a gate (leaf) clock, so it must propagate the rate change up the
clock tree, so that corresponding MUX/DIV clocks can actually change
their values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for
all USI instances in GS101 PERIC0: USI{1-8, 14}. This change involves the
following clocks:

PERIC0 USI*:

    Clock                              Div range    MUX Selection
    -------------------------------------------------------------------
    gout_peric0_peric0_top0_ipclk_*    -            -
    dout_peric0_usi*_usi               /1..16       -
    mout_peric0_usi*_usi_user          -            {24.5 MHz, 400 MHz}

With input clock of 400 MHz this scheme provides the following IPCLK
rate range, for each USI block:

    PERIC0 USI*:       1.5 MHz ... 400 MHz

Accounting for internal /4 divider in SPI blocks, and because the max
SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates:

    PERIC0 USI_SPI*:   384 KHz ... 49.9 MHz

Fixes: 893f133 ("clk: samsung: gs101: add support for cmu_peric0")
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: André Draszik <andre.draszik@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240419100915.2168573-2-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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@ambarus @krzk
ambarus authored and krzk committed Apr 22, 2024
1 parent 04ee3a0 commit 7b54d91
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135 changes: 72 additions & 63 deletions drivers/clk/samsung/clk-gs101.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2763,33 +2763,33 @@ static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
MUX(CLK_MOUT_PERIC0_USI0_UART_USER,
"mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI14_USI_USER,
"mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI1_USI_USER,
"mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI2_USI_USER,
"mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI3_USI_USER,
"mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI4_USI_USER,
"mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI5_USI_USER,
"mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI6_USI_USER,
"mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI7_USI_USER,
"mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_USI8_USI_USER,
"mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1),
nMUX(CLK_MOUT_PERIC0_USI14_USI_USER,
"mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1),
nMUX(CLK_MOUT_PERIC0_USI1_USI_USER,
"mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1),
nMUX(CLK_MOUT_PERIC0_USI2_USI_USER,
"mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1),
nMUX(CLK_MOUT_PERIC0_USI3_USI_USER,
"mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1),
nMUX(CLK_MOUT_PERIC0_USI4_USI_USER,
"mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1),
nMUX(CLK_MOUT_PERIC0_USI5_USI_USER,
"mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1),
nMUX(CLK_MOUT_PERIC0_USI6_USI_USER,
"mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1),
nMUX(CLK_MOUT_PERIC0_USI7_USI_USER,
"mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1),
nMUX(CLK_MOUT_PERIC0_USI8_USI_USER,
"mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p,
PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1),
};

static const struct samsung_div_clock peric0_div_clks[] __initconst = {
Expand All @@ -2798,33 +2798,42 @@ static const struct samsung_div_clock peric0_div_clks[] __initconst = {
DIV(CLK_DOUT_PERIC0_USI0_UART,
"dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 4),
DIV(CLK_DOUT_PERIC0_USI14_USI,
"dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4),
DIV(CLK_DOUT_PERIC0_USI1_USI,
"dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4),
DIV(CLK_DOUT_PERIC0_USI2_USI,
"dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4),
DIV(CLK_DOUT_PERIC0_USI3_USI,
"dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4),
DIV(CLK_DOUT_PERIC0_USI4_USI,
"dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4),
DIV(CLK_DOUT_PERIC0_USI5_USI,
"dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4),
DIV(CLK_DOUT_PERIC0_USI6_USI,
"dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4),
DIV(CLK_DOUT_PERIC0_USI7_USI,
"dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4),
DIV(CLK_DOUT_PERIC0_USI8_USI,
"dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4),
DIV_F(CLK_DOUT_PERIC0_USI14_USI,
"dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI1_USI,
"dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI2_USI,
"dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI3_USI,
"dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI4_USI,
"dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI5_USI,
"dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI6_USI,
"dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI7_USI,
"dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI8_USI,
"dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
};

static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
Expand Down Expand Up @@ -2857,11 +2866,11 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0,
"gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
21, 0, 0),
21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1,
"gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
21, 0, 0),
21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10,
"gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
Expand Down Expand Up @@ -2889,27 +2898,27 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2,
"gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
21, 0, 0),
21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3,
"gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
21, 0, 0),
21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4,
"gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
21, 0, 0),
21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5,
"gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
21, 0, 0),
21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6,
"gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
21, 0, 0),
21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7,
"gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
21, 0, 0),
21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8,
"gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
Expand Down Expand Up @@ -2990,7 +2999,7 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2,
"gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2,
21, 0, 0),
21, CLK_SET_RATE_PARENT, 0),
/* Disabling this clock makes the system hang. Mark the clock as critical. */
GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0,
"gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user",
Expand Down
11 changes: 9 additions & 2 deletions drivers/clk/samsung/clk.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -133,17 +133,24 @@ struct samsung_mux_clock {
.name = cname, \
.parent_names = pnames, \
.num_parents = ARRAY_SIZE(pnames), \
.flags = (f) | CLK_SET_RATE_NO_REPARENT, \
.flags = f, \
.offset = o, \
.shift = s, \
.width = w, \
.mux_flags = mf, \
}

#define MUX(_id, cname, pnames, o, s, w) \
__MUX(_id, cname, pnames, o, s, w, 0, 0)
__MUX(_id, cname, pnames, o, s, w, CLK_SET_RATE_NO_REPARENT, 0)

#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
__MUX(_id, cname, pnames, o, s, w, (f) | CLK_SET_RATE_NO_REPARENT, mf)

/* Used by MUX clocks where reparenting on clock rate change is allowed. */
#define nMUX(_id, cname, pnames, o, s, w) \
__MUX(_id, cname, pnames, o, s, w, 0, 0)

#define nMUX_F(_id, cname, pnames, o, s, w, f, mf) \
__MUX(_id, cname, pnames, o, s, w, f, mf)

/**
Expand Down

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