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drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
This patch adds an initial DRM driver for the Mediatek MT8173 DISP subsystem. It currently supports two fixed output streams from the OVL0/OVL1 sources to the DSI0/DPI0 sinks, respectively. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: YT Shen <yt.shen@mediatek.com> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Signed-off-by: Mao Huang <littlecvr@chromium.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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config DRM_MEDIATEK | ||
tristate "DRM Support for Mediatek SoCs" | ||
depends on DRM | ||
depends on ARCH_MEDIATEK || (ARM && COMPILE_TEST) | ||
select DRM_GEM_CMA_HELPER | ||
select DRM_KMS_HELPER | ||
select IOMMU_DMA | ||
select MEMORY | ||
select MTK_SMI | ||
help | ||
Choose this option if you have a Mediatek SoCs. | ||
The module will be called mediatek-drm | ||
This driver provides kernel mode setting and | ||
buffer management to userspace. |
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mediatek-drm-y := mtk_disp_ovl.o \ | ||
mtk_disp_rdma.o \ | ||
mtk_drm_crtc.o \ | ||
mtk_drm_ddp.o \ | ||
mtk_drm_ddp_comp.o \ | ||
mtk_drm_drv.o \ | ||
mtk_drm_fb.o \ | ||
mtk_drm_gem.o \ | ||
mtk_drm_plane.o | ||
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obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o |
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/* | ||
* Copyright (c) 2015 MediaTek Inc. | ||
* | ||
* This program is free software; you can redistribute it and/or modify | ||
* it under the terms of the GNU General Public License version 2 as | ||
* published by the Free Software Foundation. | ||
* | ||
* This program is distributed in the hope that it will be useful, | ||
* but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
* GNU General Public License for more details. | ||
*/ | ||
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#include <drm/drmP.h> | ||
#include <linux/clk.h> | ||
#include <linux/component.h> | ||
#include <linux/of_device.h> | ||
#include <linux/of_irq.h> | ||
#include <linux/platform_device.h> | ||
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#include "mtk_drm_crtc.h" | ||
#include "mtk_drm_ddp_comp.h" | ||
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#define DISP_REG_OVL_INTEN 0x0004 | ||
#define OVL_FME_CPL_INT BIT(1) | ||
#define DISP_REG_OVL_INTSTA 0x0008 | ||
#define DISP_REG_OVL_EN 0x000c | ||
#define DISP_REG_OVL_RST 0x0014 | ||
#define DISP_REG_OVL_ROI_SIZE 0x0020 | ||
#define DISP_REG_OVL_ROI_BGCLR 0x0028 | ||
#define DISP_REG_OVL_SRC_CON 0x002c | ||
#define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n)) | ||
#define DISP_REG_OVL_SRC_SIZE(n) (0x0038 + 0x20 * (n)) | ||
#define DISP_REG_OVL_OFFSET(n) (0x003c + 0x20 * (n)) | ||
#define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n)) | ||
#define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) | ||
#define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) | ||
#define DISP_REG_OVL_ADDR(n) (0x0f40 + 0x20 * (n)) | ||
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#define OVL_RDMA_MEM_GMC 0x40402020 | ||
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#define OVL_CON_BYTE_SWAP BIT(24) | ||
#define OVL_CON_CLRFMT_RGB565 (0 << 12) | ||
#define OVL_CON_CLRFMT_RGB888 (1 << 12) | ||
#define OVL_CON_CLRFMT_RGBA8888 (2 << 12) | ||
#define OVL_CON_CLRFMT_ARGB8888 (3 << 12) | ||
#define OVL_CON_AEN BIT(8) | ||
#define OVL_CON_ALPHA 0xff | ||
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/** | ||
* struct mtk_disp_ovl - DISP_OVL driver structure | ||
* @ddp_comp - structure containing type enum and hardware resources | ||
* @crtc - associated crtc to report vblank events to | ||
*/ | ||
struct mtk_disp_ovl { | ||
struct mtk_ddp_comp ddp_comp; | ||
struct drm_crtc *crtc; | ||
}; | ||
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static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) | ||
{ | ||
struct mtk_disp_ovl *priv = dev_id; | ||
struct mtk_ddp_comp *ovl = &priv->ddp_comp; | ||
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/* Clear frame completion interrupt */ | ||
writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA); | ||
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if (!priv->crtc) | ||
return IRQ_NONE; | ||
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mtk_crtc_ddp_irq(priv->crtc, ovl); | ||
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return IRQ_HANDLED; | ||
} | ||
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static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp, | ||
struct drm_crtc *crtc) | ||
{ | ||
struct mtk_disp_ovl *priv = container_of(comp, struct mtk_disp_ovl, | ||
ddp_comp); | ||
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priv->crtc = crtc; | ||
writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN); | ||
} | ||
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static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp) | ||
{ | ||
struct mtk_disp_ovl *priv = container_of(comp, struct mtk_disp_ovl, | ||
ddp_comp); | ||
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priv->crtc = NULL; | ||
writel_relaxed(0x0, comp->regs + DISP_REG_OVL_INTEN); | ||
} | ||
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static void mtk_ovl_start(struct mtk_ddp_comp *comp) | ||
{ | ||
writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN); | ||
} | ||
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static void mtk_ovl_stop(struct mtk_ddp_comp *comp) | ||
{ | ||
writel_relaxed(0x0, comp->regs + DISP_REG_OVL_EN); | ||
} | ||
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static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w, | ||
unsigned int h, unsigned int vrefresh) | ||
{ | ||
if (w != 0 && h != 0) | ||
writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE); | ||
writel_relaxed(0x0, comp->regs + DISP_REG_OVL_ROI_BGCLR); | ||
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writel(0x1, comp->regs + DISP_REG_OVL_RST); | ||
writel(0x0, comp->regs + DISP_REG_OVL_RST); | ||
} | ||
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static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx) | ||
{ | ||
unsigned int reg; | ||
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writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx)); | ||
writel(OVL_RDMA_MEM_GMC, comp->regs + DISP_REG_OVL_RDMA_GMC(idx)); | ||
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reg = readl(comp->regs + DISP_REG_OVL_SRC_CON); | ||
reg = reg | BIT(idx); | ||
writel(reg, comp->regs + DISP_REG_OVL_SRC_CON); | ||
} | ||
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static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx) | ||
{ | ||
unsigned int reg; | ||
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reg = readl(comp->regs + DISP_REG_OVL_SRC_CON); | ||
reg = reg & ~BIT(idx); | ||
writel(reg, comp->regs + DISP_REG_OVL_SRC_CON); | ||
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writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx)); | ||
} | ||
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static unsigned int ovl_fmt_convert(unsigned int fmt) | ||
{ | ||
switch (fmt) { | ||
default: | ||
case DRM_FORMAT_RGB565: | ||
return OVL_CON_CLRFMT_RGB565; | ||
case DRM_FORMAT_BGR565: | ||
return OVL_CON_CLRFMT_RGB565 | OVL_CON_BYTE_SWAP; | ||
case DRM_FORMAT_RGB888: | ||
return OVL_CON_CLRFMT_RGB888; | ||
case DRM_FORMAT_BGR888: | ||
return OVL_CON_CLRFMT_RGB888 | OVL_CON_BYTE_SWAP; | ||
case DRM_FORMAT_RGBX8888: | ||
case DRM_FORMAT_RGBA8888: | ||
return OVL_CON_CLRFMT_ARGB8888; | ||
case DRM_FORMAT_BGRX8888: | ||
case DRM_FORMAT_BGRA8888: | ||
return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; | ||
case DRM_FORMAT_XRGB8888: | ||
case DRM_FORMAT_ARGB8888: | ||
return OVL_CON_CLRFMT_RGBA8888; | ||
case DRM_FORMAT_XBGR8888: | ||
case DRM_FORMAT_ABGR8888: | ||
return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; | ||
} | ||
} | ||
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static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, | ||
struct mtk_plane_state *state) | ||
{ | ||
struct mtk_plane_pending_state *pending = &state->pending; | ||
unsigned int addr = pending->addr; | ||
unsigned int pitch = pending->pitch & 0xffff; | ||
unsigned int fmt = pending->format; | ||
unsigned int offset = (pending->y << 16) | pending->x; | ||
unsigned int src_size = (pending->height << 16) | pending->width; | ||
unsigned int con; | ||
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if (!pending->enable) | ||
mtk_ovl_layer_off(comp, idx); | ||
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con = ovl_fmt_convert(fmt); | ||
if (idx != 0) | ||
con |= OVL_CON_AEN | OVL_CON_ALPHA; | ||
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writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx)); | ||
writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx)); | ||
writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx)); | ||
writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx)); | ||
writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(idx)); | ||
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if (pending->enable) | ||
mtk_ovl_layer_on(comp, idx); | ||
} | ||
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static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = { | ||
.config = mtk_ovl_config, | ||
.start = mtk_ovl_start, | ||
.stop = mtk_ovl_stop, | ||
.enable_vblank = mtk_ovl_enable_vblank, | ||
.disable_vblank = mtk_ovl_disable_vblank, | ||
.layer_on = mtk_ovl_layer_on, | ||
.layer_off = mtk_ovl_layer_off, | ||
.layer_config = mtk_ovl_layer_config, | ||
}; | ||
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static int mtk_disp_ovl_bind(struct device *dev, struct device *master, | ||
void *data) | ||
{ | ||
struct mtk_disp_ovl *priv = dev_get_drvdata(dev); | ||
struct drm_device *drm_dev = data; | ||
int ret; | ||
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ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp); | ||
if (ret < 0) { | ||
dev_err(dev, "Failed to register component %s: %d\n", | ||
dev->of_node->full_name, ret); | ||
return ret; | ||
} | ||
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return 0; | ||
} | ||
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static void mtk_disp_ovl_unbind(struct device *dev, struct device *master, | ||
void *data) | ||
{ | ||
struct mtk_disp_ovl *priv = dev_get_drvdata(dev); | ||
struct drm_device *drm_dev = data; | ||
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mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp); | ||
} | ||
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static const struct component_ops mtk_disp_ovl_component_ops = { | ||
.bind = mtk_disp_ovl_bind, | ||
.unbind = mtk_disp_ovl_unbind, | ||
}; | ||
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static int mtk_disp_ovl_probe(struct platform_device *pdev) | ||
{ | ||
struct device *dev = &pdev->dev; | ||
struct mtk_disp_ovl *priv; | ||
int comp_id; | ||
int irq; | ||
int ret; | ||
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | ||
if (!priv) | ||
return -ENOMEM; | ||
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irq = platform_get_irq(pdev, 0); | ||
if (irq < 0) | ||
return irq; | ||
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ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler, | ||
IRQF_TRIGGER_NONE, dev_name(dev), priv); | ||
if (ret < 0) { | ||
dev_err(dev, "Failed to request irq %d: %d\n", irq, ret); | ||
return ret; | ||
} | ||
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comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_OVL); | ||
if (comp_id < 0) { | ||
dev_err(dev, "Failed to identify by alias: %d\n", comp_id); | ||
return comp_id; | ||
} | ||
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ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, | ||
&mtk_disp_ovl_funcs); | ||
if (ret) { | ||
dev_err(dev, "Failed to initialize component: %d\n", ret); | ||
return ret; | ||
} | ||
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platform_set_drvdata(pdev, priv); | ||
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ret = component_add(dev, &mtk_disp_ovl_component_ops); | ||
if (ret) | ||
dev_err(dev, "Failed to add component: %d\n", ret); | ||
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return ret; | ||
} | ||
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static int mtk_disp_ovl_remove(struct platform_device *pdev) | ||
{ | ||
component_del(&pdev->dev, &mtk_disp_ovl_component_ops); | ||
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return 0; | ||
} | ||
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static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { | ||
{ .compatible = "mediatek,mt8173-disp-ovl", }, | ||
{}, | ||
}; | ||
MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); | ||
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struct platform_driver mtk_disp_ovl_driver = { | ||
.probe = mtk_disp_ovl_probe, | ||
.remove = mtk_disp_ovl_remove, | ||
.driver = { | ||
.name = "mediatek-disp-ovl", | ||
.owner = THIS_MODULE, | ||
.of_match_table = mtk_disp_ovl_driver_dt_match, | ||
}, | ||
}; |
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